Optimal module set and clock cycle selection for DSP synthesis

Chen, Liang-GeeLiang-GeeChenJeng, Lih-GwoLih-GwoJengLIANG-GEE CHEN2018-09-102018-09-101991http://www.scopus.com/inward/record.url?eid=2-s2.0-0026264707&partnerID=MN8TOARShttp://scholars.lib.ntu.edu.tw/handle/123456789/292105Optimal module set and clock cycle selection for DSP synthesisconference paper