指導教授：胡振國臺灣大學：電子工程學研究所曾柏皓Tseng, Po-HaoPo-HaoTseng2014-11-302018-07-102014-11-302018-07-102014http://ntur.lib.ntu.edu.tw//handle/246246/263856本論文利用陽極氧化法特有之電場效應，於經電子束定義並蝕刻之矽基板上成功形成自我對準之雙層單晶矽奈米線，研究得到寬度9nm之單晶矽奈米線。並利用此氧化方法成長超薄氧化層於非平面矽基板上，將其製作成不同閘極面積之非平面電容元件並探討元件之電特性行為。我們比較傳統平面電容元件與非平面電容元件從空乏區至深空乏區之電容-電壓響應。在非平面元件中，由於元件空乏區之耦合效應，將導致突起稜角處呈現較寬的空乏區寬度。在元件進入強反轉時，由於非平面稜角處將會聚集較多的少數載子，因此產生明顯的低頻響應。此外，非平面元件在不同的閘極面積下將呈現不均勻之深空乏行為，而平面元件則與閘極面積相依。我們更利用高低頻電容法萃取元件之介面缺陷特性，由於非平面電容元件存在非(100)之晶向，因此展現介面缺陷重分佈行為。在平面電容元件將由類施體介面缺陷主導，而非平面元件則會同時擁有類施體及類受體兩種介面缺陷種類。在非平面結構中之凸起及凹起稜角處，其氧化層電場也呈現不均勻之分佈，導致非平面元件經過穩定度測試後之飽和電流行為與平面元件具有差異。最後，我們也利用突起稜角處之增強式空乏區寬度，將超薄氧化層之非平面電容元件應用於光電容偵測器，實驗發現在照光強度為90mW/cm2下，非平面元件可增強至85.5%之光電容敏感度，而平面元件之光電容敏感度約為7%。We demonstrated the self-aligned double layers single crystal silicon nanowires in silicon substrate by the control of the electric field effect of anodic oxidation. The wire pattern was defined by E-beam lithography and was etched by reactive ion etching. The minimum width of single crystal Si nanowire is around 9 nm. The electrical characteristics of non-planar substrate MOS capacitors with ultra thin oxides and different gate areas are also studied and discussed in this work. The capacitance-voltage (C-V) responses of non-planar and planar MOS capacitors are comprehensively studied by comparing their C-V behaviors from depletion to DD regions. The convex corner exhibits broader depletion width (WD) due to the coupling effect. The minority carrier will also be crowded in the non-planar corner and therefore introduce obvious extra low frequency effect in strong inversion region. Moreover, the non-uniform deep depletion (DD) behaviors for non-planar sample and the area dependent DD for planar sample are observed. It is also noticed that the characteristics of interface trap was observed by applying the combined high-low frequency capacitance method. The non-planar MOS exhibits redistribution behaviors of interface trap due to the non-(100) orientation effect. In the planar samples, the major type of interface traps is donor-like. However, both of donor-like and acceptor-like interface traps are existed in non-planar sample as compared with the planar one. After the stress treatment, the non-uniform oxide electric fields in concave and convex corners are responsible for the irregular saturation tunneling current behavior in non-planar samples which is different from planar one. Finally, the non-planar substrate metal-oxide-semiconductor (MOS) photo-capacitance detector with enhanced deep depletion (DD) at convex corner was also demonstrated in this work. It was found that the significant enhanced photo-capacitance variation sensitivity (ΔC/C) of 85.5% was achieved for non-planar MOS device which respect to that of 7% for planar one under the same illumination intensity of 90mW/cm2.Abstract (Chinese)……………………………………………………I Abstract (English) ……………..………………………………………..III Content………………………................................................……............V Figure Captions………………........……………...........………............VII Table Captions…………………….......……….......……………........XV Chapter 1 Introduction...............................................................................1 1-1 Semiconductor industry development…………………..………...........1 1-2 Emerging research on non-planar substrate devices …….……….........3 1-3 About this work……………………………………….………………..6 Chapter 2 Device Development and Processes………………………...13 2-1 Mechanism and system of anodic oxidation……………………...…..13 2-2 Non-uniform electric field induced oxide profiles variation…………15 2-3 Formation of single crystal Si nanowire by anodic oxidation………..16 2-4 Fabrication of non-planar MOS device……………………………….22 2-5 Summary………………………………………………………..…….25 Chapter 3 Electrical Characteristics of Non-planar MOS Device……33 3-1 Behaviors of tunneling current………………………………………..33 3-2 Capacitance-voltage response of non-planar MOS devices…………..35 3-2-1 Capacitance-voltage response before and after stress treatment.35 3-2-2 Deep depletion behavior in different oxide thicknesses………..37 3-2-3 Deep depletion behavior in different gate areas………………..38 3-2-4 Capacitance-voltage response before and after stress treatment.40 3-3 Interface trap capacitance of non-planar MOS device………………..43 3-3-1 Distribution behavior of interface trap capacitance…………….43 3-3-2 Thicknesses dependent interface trap capacitance distribution behavior………………………………………………………...45 3-3-3 Area dependent interface trap capacitance distribution behavior………………………………………………………...46 3-4 Non-uniform electric field effect on electrical reliability…………….49 3-4-1 Irregular inversion tunneling current behavior………………..49 3-4-2 Stress induced irregular interface trap characteristic………….52 3-5 Summary ……………………………………………………………..52 Chapter 4 Non-planar Substrate MOS Photo-Capacitance Detectors.69 4-1 Introduction…………………………………………………………...69 4-2 Enhanced photo-capacitance variation sensitivity in deep depletion region……………………………………………………………………...71 4-3 Thicknesses dependent photo-capacitance sensitivity………………..72 4-4 Area dependent photo-capacitance sensitivity………………………..73 4-5 Summary ……………………………………………………………..75 Chapter 5 Conclusion and Suggestion for Future Work……………...83 5-1 Conclusion…………………………………...……………………….83 5-2 Suggestion for future work…………………………...………………85 Reference………………………………………………………...……….87 Publication List…………………………………………………………..978219599 bytesapplication/pdf論文公開時間：2019/07/22論文使用權限：同意有償授權(權利金給回饋學校)奈米線非平面電容元件深空乏介面缺陷光電容偵測器thesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/263856/1/ntu-103-D99943017-1.pdf