Hsieh, H.-H.H.-H.HsiehChen, H.-S.H.-S.ChenHung, P.-H.P.-H.HungLIANG-HUNG LU2020-06-112020-06-11201110638210https://scholars.lib.ntu.edu.tw/handle/123456789/498190https://www.scopus.com/inward/record.uri?eid=2-s2.0-79953101276&doi=10.1109%2fTVLSI.2009.2037885&partnerID=40&md5=0f7a0b06a5b2dba4d29bc08cb3b9e5d8This paper presents experimental CMOS RF frontends suitable for ultra-low-power and ultra-low-voltage operations. In order to achieve the desirable gain and linearity of the receiver chain at a reduced supply voltage, the current-reused bias technique and the multiple-gated transistors are employed. As for the transmitter frontend, a low-voltage double-balanced mixer is utilized to maximize the conversion gain. In addition, a differential-to- single-ended circuit is also included to increase the saturated output power. Using a standard 0.18-μm CMOS process, the proposed circuits are realized for 5-GHz RF applications with a supply voltage of 0.6 V. The fabricated receiver frontend demonstrates a conversion gain of 14.5 dB and an IIP3 of -16 dBm with a power consumption of 2.1 mW, while the conversion gain and the output 1-dB compression of the transmitter frontend are 12.9 dB and -4.1 dBm, respectively, provided a dc power of 6 mW. © 2006 IEEE.CMOS RFIC; current-reused bias technique; low-power; low-voltage; moderate inversion; multiple-gated transistors; receiver frontend; transmitter frontendCMOS RFIC; current-reused bias technique; Low Power; Low-voltage; Moderate inversion; multiple-gated transistors; receiver frontend; CMOS integrated circuits; DC power transmission; Transmitters; Bias voltagejournal article10.1109/TVLSI.2009.20378852-s2.0-79953101276