陳信樹臺灣大學：電子工程學研究所林俊成Lin, Jyun-ChengJyun-ChengLin2007-11-272018-07-102007-11-272018-07-102007http://ntur.lib.ntu.edu.tw//handle/246246/57332在傳統的連續逼近式延遲鎖相迴路中，由於響應時間的關係，鎖定時間仍然大大地增加，為了改善鎖定速度，本論文提出一個數位延遲鎖相迴路，可以達到低功率且快速鎖定的特性。本晶片使用台積電0.13-μm 1P8M CMOS 製程製作，晶片面積為0.77 x 0.79mm2，核心面積為0.226 x 0.076mm2，操作頻率範圍從50MHz到200MHz，在最高操作頻率下，量測到的功率消耗為0.259mW，鎖定時間為4個時脈週期，當操作頻率為200MHz的時候，量測到的方均根抖動和峰值抖動分別是3.67ps和34.17ps。In conventional SARDLL, the lock time still increases seriously because of the response time. A digital DLL is proposed in this work to improve the locking speed. The proposed DLL can exhibit features of low-power and fast-lock. This work is fabricated in TSMC 0.13-μm 1P8M CMOS technology. The chip area is 0.77 x 0.79mm2, and the active area is 0.226 x 0.076mm2. The proposed DLL can operate in the range from 50MHz to 200MHz. The measured power consumption is 0.259mW at the maximum operation frequency 200MHz. The lock time is 4 clock cycles. When the operation frequency is 200MHz, the measured rms jitter and peak-to-peak jitter is 3.67ps and 34.17ps, respectively.Table of Contents 摘要 I Abstract II Table of Contents III List of Figures V List of Tables VII Chapter 1 The Basic Theory of the Delay-Locked Loops......1 1.1 Introduction 1 1.2 The review of the delay-locked loop 2 1.3 The stability and the model of the DLL 4 1.3.1 Charge pump DLL model 4 1.3.2 Stability analysis 5 1.4 Jitter analysis 6 1.4.1 Jitter definition 6 1.4.2 Jitter transfer function 8 1.4.3 Jitter peaking 9 1.5 The building blocks of DLLs 10 1.5.1 Phase detector 10 1.5.2 Charge pump 12 1.5.3 Voltage-controlled delay line 16 Chapter 2 Review of Digital DLL Architectures.............19 2.1 Introduction 19 2.2 Digital DLL architectures 21 2.2.1 Register-controlled DLL 21 2.2.2 Counter-controlled DLL 22 2.2.3 SAR-controlled DLL 24 2.3 Proposed digital DLL 27 Chapter 3 A low-power fast-lock digital DLL..............28 3.1 Searching Algorithm 28 3.2 Architecture 29 3.3 Circuit Implement 32 3.3.1 Encoder 32 3.3.2 Half Delay 36 3.3.3 Delay Cell 37 3.3.4 Multiplexer 38 3.4 Simulation Results 39 Chapter 4 Test Setup and Measurement Results..............47 4.1 Test Setup 47 4.2 Print Circuit Board Layout 48 4.3 Experiment Results 51 4.4 Summary 57 Chapter 5 Conclusion and Future works.....................60 5.1 Conclusions 60 5.2 Future works 60 Bibliography..............................................625926960 bytesapplication/pdfen-US延遲鎖相迴路鎖定時間DLLlock timethesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/57332/1/ntu-96-R94943103-1.pdf