Hierarchical Timing Verification System for Multiple Clocked Logic Circuit

Tyan, C. Y.C. Y.Tyan馮武雄于惠中Yeh, T. S.T. S.YehFeng, Wu-ShiungWu-ShiungFengYu, Hui-JungHui-JungYu2009-02-042018-07-062009-02-042018-07-061986-08http://ntur.lib.ntu.edu.tw//handle/246246/121402en-USHierarchical Timing Verification System for Multiple Clocked Logic Circuitconference paper