A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay

Dept. of Electr. Eng., National Taiwan Univ.Chang, Hsiang-HuiHsiang-HuiChangLin, Jyh-WoeiJyh-WoeiLinLiu, Shen-IuanShen-IuanLiu2007-04-192018-07-062007-04-192018-07-062002-05http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021169application/pdf475525 bytesapplication/pdfen-US[SDGs]SDG7A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delayjournal article10.1109/CICC.2002.1012764http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910021169/1/01012764.pdf