Lee, Chung ChiaChung ChiaLeeYAO-WEN CHANG2024-01-312024-01-312023-01-01979835031559210923152https://scholars.lib.ntu.edu.tw/handle/123456789/639414Modern heterogeneous integration requires dense IO interconnections among chips, such as CPU and memory, to facilitate bandwidth-aware packaging. The embedded multi-die interconnect bridge (EMIB) has attracted much attention recently by providing a high wiring density and low manufacturing cost. However, EMIB optimization must consider constrained wire orientations and crosstalk. This paper presents the first work on floorplanning for EMIB-based packaging. We first model the floorplanning problem for EMIB-based packaging. Based on a hybrid structure of transitive closure graphs and B∗-trees, we present a novel simulated-annealing-based algorithm to efficiently generate the desired EMIB-aware floorplans. We employ maximum-spanning-tree-based partitioning and tree-based classification for already found partial topologies to search for desired solutions more efficiently. Experimental results show that our algorithm can significantly improve the area, total wirelength, and computation time compared with simulated annealing based on TCGs alone.[SDGs]SDG9conference paper10.1109/ICCAD57390.2023.103236092-s2.0-85181401082https://api.elsevier.com/content/abstract/scopus_id/85181401082