AN-YEU(ANDY) WU2022-05-192022-05-1920209.78173E+12https://www.scopus.com/inward/record.uri?eid=2-s2.0-85090243289&doi=10.1109%2fVLSICircuits18222.2020.9163022&partnerID=40&md5=b2a07131dd1933e72a742cecf710dbcdhttps://scholars.lib.ntu.edu.tw/handle/123456789/611211To meet with the stringent requirements of ultra-low latency communication in 5G, this work presents a polar decoder fabricated in TSMC 40nm CMOS featuring: 1) World's first neural network-assisted decoder chip with 8× improvement of convergence rate. 2) Fully reconfigurable architecture to support multi-code length operations with a 2-to-8× hardware utilization rate. 3) Optimized fixed-point design of processing element (PE) to reduce 73% area and 67% power consumption. © 2020 IEEE.[SDGs]SDG75G mobile communication systems; Decoding; Network coding; Reconfigurable architectures; VLSI circuits; Convergence rates; Fixed points; Hardware utilization; Low latency; Low-latency communication; Processing elements; Reconfigurable; Stringent requirement; Neural networksconference paper10.1109/VLSICircuits18222.2020.91630222-s2.0-85090243289