Chaung, Mei-ChenMei-ChenChaungKuo, Jhe-JiaJhe-JiaKuoWang, Chi-HseuhChi-HseuhWangHUEI WANG2010-10-152018-07-052010-10-152018-07-052008-05https://www.scopus.com/inward/record.uri?eid=2-s2.0-44049101764&doi=10.1109%2fLMWC.2008.922127&partnerID=40&md5=712cbdd1f343ec2accecedc25e1afe6bA fully integrated divide-by-4 frequency divider has been designed, fabricated, and measured in the standard bulk 0.18- μm complementary metal-oxide semiconductor (CMOS) technology. A newly proposed matching technique was used to eliminate the unwanted low frequency mixing terms at the common node of the circuit so as to achieve a high division ratio of 4. The frequency divider exhibits a measured operation range of 5 GHz from 45.9 to 50.9 GHz. It consumes a dc power of 7.56 mW at a 1.2 V supply in the steady state operation. The phase noise of the free running divider is -88.51 dBc/Hz at 1 MHz offset and the locked divider is -110.74 dBc/Hz at 1 MHz offset. The chip size is only 0.35 mm × 0.5 mm including the pad frame. To our knowledge, this divider has the highest operation frequency to date among the high division ratio injection-lock type frequency dividers in commercial CMOS 0.18-μm process. © 2006 IEEE.en-USComplementary metal-oxide semiconductor (CMOS) integrated circuits (ICs); Injection-locked oscillators; Millimeter-wave circuits[SDGs]SDG7journal article10.1109/LMWC.2008.9221272-s2.0-44049101764