指導教授：王勝德臺灣大學：電機工程學研究所蔡偉哲Tsai, Wei-CheWei-CheTsai2014-11-282018-07-062014-11-282018-07-062014http://ntur.lib.ntu.edu.tw//handle/246246/262879高階合成的編譯器通常可以生成幾種不同的硬體讓使用者選用，然而編譯器預設的硬體架構不可能適應所有使用者的需求。我們提出了一個使用者易於客制化的硬體架構，其中的編譯器是修改自LegUp高階合成編譯器且加上暫存記憶體來加速編譯器所產生的硬體，此外我們使用雙埠記憶體來增強效能。暫存記憶體內容的選擇則是由一個基於線性規劃的演算法來決定，此演算法在編譯時分析源始碼以求得一個最佳化的記憶體配置。實驗的結果展示使用暫存記憶體後，程式執行的時間只需原本只用SDRAM時的23%~43%，而且使用SDRAM加上暫存記憶體可以解決比較大的問題。High-level synthesis (HLS) compilers usually provide some supported target architectures that can be chosen by users; however, the limited architectures may not fit the requirements of underlying systems. In this paper, we propose a target architecture embedded with a scratchpad memory (SPM) and an SDRAM that allows users to customize their design. The proposed architecture has been integrated with an HLS compiler, called LegUp, so that the synthesizing computation can be executed on the target architecture with the SPM and the SDRAM. In addition, we use a dual port memory controller to enhance the performance of the target architecture. An algorithm based on integer linear programming is used to allocate data to the proposed SPM at compile time. The experiment results show that the proposed architecture can effectively achieve the 23%~43% execution time of an architecture without an SPM, and can solve huge problems by using the external memory.口試委員會審定書 i 摘要 ii Abstract iii Chapter 1. Introduction 1 1.1 Research object 2 1.2 Thesis organization 3 Chapter 2. Related Work 3 2.1 High level synthesis 4 2.2 Scratchpad memory 6 Chapter 3. Background 8 3.1 LLVM 8 3.2 LegUp 10 3.2.1 Hardware Architecture of LegUp 10 3.2.2 Software Architecture of LegUp 11 3.3 Quartus II compiler tool chain 12 3.3.1 Qsys System Design tool 12 3.3.2 Avalon-MM interface 13 3.4 Linear program 14 Chapter 4. Methodology 15 4.1 Design flow 15 4.2 Target Architecture 17 4.3 SPM allocation algorithm 18 4.4 Scheduler 21 4.5 Integrate the HLS compiler into Qsys 23 Chapter 5. Experiment & Results 25 5.1 Experiment setup 25 5.2 SDRAM and SPM with shared bus 25 5.3 Dual Ports architecture 27 5.4 Scratchpad memory allocation 31 5.5 Area report 35 Chapter 6. Conclusions 37 Reference 384755967 bytesapplication/pdf論文公開時間：2019/02/26論文使用權限：同意有償授權(權利金給回饋學校)高階合成編譯器暫存記憶體FPGAthesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/262879/1/ntu-103-R00921080-1.pdf