Cai Y.-JHsu YYAO-WEN CHANG2022-04-252022-04-2520210738100Xhttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85119455397&doi=10.1109%2fDAC18074.2021.9586296&partnerID=40&md5=59dd3a1fa8a1d35afe1e06b21422da58https://scholars.lib.ntu.edu.tw/handle/123456789/607514In modern packaging technology, redistribution layers (RDLs) are often used to redistribute interconnections among multiple chips and between I/O pads and bump pads. For high-density RDL routing, irregular vias, where vias can be placed at arbitrary locations, are adopted to better utilize RDL resources to obtain desired routing solutions. As the problem size increases, however, using irregular vias may suffer from high computation overheads. Moreover, most previous works route pre-assignment (PA) and free-assignment (FA) nets in separate stages, incurring routing resource competition. To remedy these disadvantages, we propose a simultaneous PA and FA routing framework with irregular RDL via planning. In this paper, we first propose a novel partitioning method based on the Voronoi diagram to handle irregular via structures and derive a theoretical upper bound on the number of generated regions. We then propose a chord-based tile model and a net-sequence list to generate non-crossing guides for PA and FA nets on the same routing graph. Finally, we develop a novel geometry-based pattern routing to obtain the final solutions. Experimental results show that our work can achieve 100% routability and an average 30X speedup over the-state-of-the-art work. ? 2021 IEEE.Computation overheadsDensity redistributionPackaging technologiesPartitioning methodsProblem sizeRedistribution layersResource competitionsRouting frameworksRouting resourcesRoutingsComputer aided designconference paper10.1109/DAC18074.2021.95862962-s2.0-85119455397