Chen W.-MYao Y.-SSHEN-IUAN LIU2023-06-092023-06-09202115498328https://www.scopus.com/inward/record.uri?eid=2-s2.0-85119492994&doi=10.1109%2fTCSI.2021.3108138&partnerID=40&md5=ce6caf8a5d08c7d4ba96cabebed3626fhttps://scholars.lib.ntu.edu.tw/handle/123456789/632356A 10.4-16-Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) is presented. The quarter-rate CDR circuit uses a pattern-based phase detector (PD) and the proposed FD. This wide-range FD is composed of a coarse FD and a fine FD (FFD) which share the same front-end comparators with the PD and the DFE. Thus, no extra comparators are required. In addition, by monitoring the drift direction of five samples on the five-bit data patterns, the FFD performs an error-free operation within a frequency error of 7.7%. Therefore, the CDR has a robust FD-to-PD transition. By using the proposed FD, this CDR circuit not only achieves a wide frequency capture range of 43%, but also has a short frequency settling time of 680mu text{s}. This CDR circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.1004 mm2. The total power of the receiver is 39.9mW at 16 Gb/s, and the calculated energy efficiency is 2.49pJ/b. © 2004-2012 IEEE.Baud-rate; clock and data recovery; decision feedback equalizer; frequency detector; low-overhead[SDGs]SDG7Clocks; Comparators (optical); Decision feedback equalizers; Energy efficiency; Feedback; Finite difference method; Phase comparators; Baud rate; Clock and data recovery; Clock recovery circuits; Data recovery circuits; Decision-feedback equalizers; Digital clocks; Digital datas; Frequency detectors; Low overhead; Phase detectors; Clock and data recovery circuits (CDR circuits)journal article10.1109/TCSI.2021.31081382-s2.0-85119492994