曹恆偉臺灣大學：電信工程學研究所杜顏廷Tu, Yen-TingYen-TingTu2007-11-272018-07-052007-11-272018-07-052007http://ntur.lib.ntu.edu.tw//handle/246246/58719本論文主要內容，在降低複雜度與提高系統效能的目標下，提出適用在百億位元乙太網路系統(10GBASE-T Ethernet System, IEEE 802.3an)的三種實體層收發機架構，分別為傳統收發機架構、以多輸入多輸出之決策回饋等化器/多輸入多輸出之湯林森-河洛緒預編碼器為基礎的收發機架構以及利用通道長度縮短技術的收發機架構。接收機後端的數位訊號處理部分，通道等化機制以及干擾消除，採用最小均方差演算法搭配多種提出的訓練方法及時的可適性調整；且在資料模式下，提出對遠端串音干擾的議題進行分析和研究，衍生出在傳送端以及接收端消除遠端串擾的兩種架構。為使系統功能更加完整，對自動增益控制的設計、數位類比轉換器和類比數位轉換器解析度的需求進行探討。時脈回復議題上雖然只有初步的分析，也已針對採用多相位時脈為基礎的時脈回復演算法上分析時脈相位解析度。 由於在百億位元乙太網路系統的高速傳輸標準下，收發機架構中的數位和類比電路都是設計上的困難與挑戰，因此，複雜度與實現的難易度在設計整體架構中成為被納入考量的重點。由最後的模擬結果得知，在提出的各類型收發機架構中，決策點訊雜比以及符元錯誤率都有很不錯的表現。In this thesis, the issues about cost down and performance improvement for 10GBASE-T Ethernet transceiver are emphasized. Three transceiver architectures are presented, including conventional transceiver architecture, transceiver architecture design based on multi-input multi-output decision feedback equalizer (MIMO-DFE)/multi-input multi-output Tomlinson-Harashima precoding (MIMO-THP) and transceiver architecture design based on channel shortening technique. Joint adaptive channel equalization and interference cancellation with proposed training methods are used to improve decision point SNR (dpSNR). Furthermore, two different architectures are presented for canceling FEXT interference at the transmitter and receiver sides during data mode, respectively. Moreover, automatic gain control (AGC) design and the resolutions of digital-to-analog converter (DAC)/analog-to-digital converter (ADC) are taken into consideration to make the whole investigation more complete. Evaluation of required phase resolution for the multi-phase clock, which will be adopted in the timing recovery mechanism, is also discussed. The digital and analog circuits under high speed data transmission are very critical for 10GBASE-T Ethernet system, so the complexity and implementation issues are also considered specifically.Chinese Abstract i Abstract iii Contents v List of Figures vii List of Tables xi Chapter 1 Introduction 1 1.1 Motivation and Goal 1 1.1.1 Characteristics and Challenges of 10GBASE-T 1 1.2 Organization of the Thesis 3 Chapter 2 Channel Model 5 2.1 Channel Impairments 6 2.1.1 Insertion Loss 6 2.1.2 Echo Interference 6 2.1.3 Near-End Crosstalk 7 2.1.4 Far-End Crosstalk 7 2.1.5 Alien Crosstalk 8 2.1.6 Other Non-Ideal Effects 8 2.2 Channel Modeling 9 Chapter 3 An Overview of 10GBASE-T Ethernet System 15 3.1 Overview 15 3.1.1 Objectives 16 3.1.2 Operation of 10GBASE-T 17 3.2 Conventional Transceiver Architecture 18 3.2.1 64B/65B Scrambler/De-Scrambler 20 3.2.2 Low Density Parity Check Encoder/Decoder 22 3.2.3 Double SQuare 128 23 3.2.4 Tomlinson-Harashima Precoding 25 3.2.5 Analog Front-End 26 3.2.6 DSP Issues of Equalization and Cancellation 26 3.2.7 Training Frame 27 3.2.8 Analysis of Background Noise 29 3.3 VLSI Challenges of Digital and Analog Circuits Design 30 3.3.1 Digital Part 31 3.3.2 Analog Part 32 Chapter 4 Transceiver Architecture Design for 10GBASE-T Ethernet System 33 4.1 Channel Equalization and Interference Cancellation 34 4.1.1 Inter-Symbol Interference 34 4.1.2 Decision Feedback Equalizer 35 4.1.3 Multi-input Multi-output Decision Feedback Equalizer 37 4.1.4 Tomlinson-Harashima Precoding Equalization 39 4.1.5 Channel Shortening Technique 42 4.2 Transceiver Architecture Design Based on Conventional Approach 45 4.2.1 Analysis of Decision Feedback Equalizer 45 4.2.2 Analysis of Echo/NEXT/FEXT Interference 48 4.2.3 Design Concept of Transceiver Architecture 49 4.2.4 Simulation Results 57 4.3 Transceiver Architecture Design Based on MIMO-DFE/MIMO-THP 63 4.3.1 Design Concept of Transceiver Architecture 63 4.3.2 Simulation Results 70 4.4 Transceiver Architecture Design Based on Channel Shortening Technique 79 4.4.1 Design Concept of Transceiver Architecture 79 4.4.2 Simulation Results 82 Chapter 5 Performance Analysis and System Simulation 87 5.1 Analyze the Resolutions of DAC and ADC 87 5.2 Automatic Gain Control 89 5.3 Loop Timing Configuration 93 5.4 System Simulation 97 Chapter 6 Conclusions and Future Works 101 6.1 Conclusions 101 6.2 Future Works 102 Appendix 103 A.1 Optimal Solution of the MMSE-DFE 103 A.2 Optimal Solution of the MMSE MIMO-DFE 105 A.3 Optimal Solution of the Optimal Shortening 106 A.4 Optimal Solution of Joint Optimal Shortening 109 Bibliography 1114102743 bytesapplication/pdfen-US百億位元乙太網路收發機等化預編碼串音干擾自動增益控制時脈回復10GBASE-T (IEEE 802.3an) Ethernet SystemTransceiverEqualizationPrecodingCrosstalkAutomatic Gain ControlClock Data Recoverythesishttp://ntur.lib.ntu.edu.tw/bitstream/246246/58719/1/ntu-96-R93942122-1.pdf