國立臺灣大學電子工程學研究所張耀文2006-07-262018-07-102006-07-262018-07-102003-07-31http://ntur.lib.ntu.edu.tw//handle/246246/19982http://ntur.lib.ntu.edu.tw/bitstream/246246/19982/1/912215E002036.pdf對於深次微米，高效能電路，當在決定電路延遲時間，電感的效應伴演著一個非常重要的角色。在本 計畫中，我們推導出一個準確的公式來模擬晶片階層之高速電路延遲模型 (buffered RLY/RLC wires and trees)。我們的公式可以處理平衡與非平衡的電路 (balanced and un-balanced trees) 且考慮加入緩衝器 (buffer insertion)，並根據180nm的製程技術 (technology)。For deep-submicron, high-performance circuits, the inductive effect plays a very important role in determining the circuit delay. In this project, we derive accurate formulae for modeling the delays of buffered RLY/RLC wires and trees. Our formulae can handle balanced and un-balanced trees and consider buffer insertion based on the 180 nm technologyapplication/pdf258680 bytesapplication/pdfzh-TW國立臺灣大學電子工程學研究所Balanced and un-balanced treesbuffer平衡與非平衡的電路緩衝器reporthttp://ntur.lib.ntu.edu.tw/bitstream/246246/19982/1/912215E002036.pdf