馮武雄臺灣大學：電機工程學研究所舒英豪Shu, Ying-HawYing-HawShu2007-11-262018-07-062007-11-262018-07-062005http://ntur.lib.ntu.edu.tw//handle/246246/52978傳統的雙邊緣觸發器(Double-Edge-Triggered Flip-Flop)是由兩組相似的單邊緣觸發器建構而成，用於管線控制電路時，雖然可以藉由雙邊觸發的方式提升電路的工作效率，但是雙倍的電路也意謂著雙倍的面積與雙倍的能源消耗。相對而言，使用互斥非或閘(XNOR)所建構的雙邊緣觸發器，會因為使用XNOR產生時脈時(Clock)所必需的間延遲，降低整體的工作速率。本篇論文中論述一個特別的XNOR，因著這樣的XNOR對於前端驅動能力的敏感，使之因輸入驅動力能力的不同，產生輸入訊號的時間差異，進而產生一組對稱之脈衝訊號，用以啟動後端的開關式閂鎖電路(Transparent Latch)。論文中所使用的開關式閂鎖電路，因為電路中的閂鎖是經由控制脈衝訊號同歩開關，大幅的提升了整體電路的反應時間。我們更進一步將此一改良的雙邊緣觸發電路，用於建構一個兩相位的管線控制電路，並以台積電所提供的0.25u製程的模型參數，在HSPICE程式下驗證電路在管線控制系統中的性能。電路模擬的結果顯示，此一改良的雙邊緣觸發電路在電力消耗及工作速率上，都優於近期發表的電路。 一般而言，非同步兩相位管線控制電路，會比傳統的非同步位四相管線控制電路來得有效率，但是在傳統的管線控制電路中必需使用一特殊的C-element，此一C-element電路經過多次的改進，在一般的單輸出入的管線控制中，具有省電、簡單、且可以避免時序錯亂的優點；但是若將此一電路當作一般的邏輯電路，在多重輸出入的管線控制電路使用時，往往會因為這樣的控制單元，是使用多層的C-element串疊而成，而大幅降低了最高運作速度。由於對稱性(Symmetric)的C-element己經免除了內部閂鎖電路所可能造成的時間延遲及能量損耗，藉由串疊時的內部邏輯的重新安排，我們不但更進一步的簡化Symmetric C-element在串疊時的電路，也縮短了訊號的路徑，有效地提升了電路的效能。同時我們也修改了一個藉由閂鎖電路所建構的非或閘(NOR)式四相位管線控制電路，藉由C-element完整順序邏輯控的制能力，我們完全移除了原有的閂鎖電路，不但提升了電路的反應時間，也降低了功率消耗。同樣的，我們也將這兩個兩相位及四相位的管線控制電路，在台積電的HSPICE模型中評估他們的優缺點。模擬結果驗證了我們的想法，大幅度簡化控制電路，並且避免使用閂鎖電路可以有效降低功率的損耗，並提升反應速度。The conventional approach of double-edge-triggered flip-flops is to have two similar edge-triggered latches. And the achieved faster speed is at the cost of double chip area and complex logic structure. By contrast, the XNOR based approaches is difficult to reach the speed demand due to the delay of the XNOR based clock generator. This paper proposes a new designed double-edge-triggered flip-flop based on an alternative XNOR gate. By utilizing the sensitivity to the driving capacity of the previous stage, we use this simplified XNOR gate as a pulse-generator. A modified transparent latch following the pulse-generator acts as an XNOR-based DET-FF, which accomplishes the almost same speed and less power dissipation as compared with two conventional DET-FFs under HSPICE simulation. We also implemented the XNOR-based DET-FF in a two-phase-pipeline system, and the HSPICE simulation in the TSMC 0.25um CMOS process shows our proposed DET-FF is much faster than those two conventional DET-FFs. Asynchronous modules operating under two-phase micro-pipeline methodology are faster than those in common four-phase control schemes because the double-edge-triggered flip-flops in the two-phase control systems capture data twice within each clock cycle. But the conventional systems with multi-port modules normally suffer from long signal paths on stacked C-elements. NOR-based control schemes provide an alternative solution to problems such as propagation delay. This paper presents two modified designs from the common two-phase and alternative NOR-based four-phase pipeline system. The HSPICE performs the evaluation based on TSMC 0.25um fast-mode CMOS model, and HSPICE simulation results show that the two-phase pipelined system is still a reliable solution with a limited number of inputs even when the theoretically lower control overhead is disregarded. A power reduction of over 27% and a propagation improvement of more than 11% are achieved by replacing some decision circuits with modified C-elements.Contents Abstract Chapter 1 Introduction 1.1 The GALS Concept ······································································· 2 1.2 Pipelined Control System—Two-Phase and Four-Phase······ 7 1.3 Organization ·················································································· 13 Chapter 2 Double-Edge-Triggered Flip-Flops 2.1 Previous Approaches ···································································· 14 2.2 XNOR Gate and Double-Edge-Triggered Flip-Flops ·············· 19 2.2-1 Alternative XNOR Gate ····················································· 20 2.2-2 Fast Transparent Latch ···················································· 22 2.3 Two-Phase Pipelined System ······················································ 25 2.3-1 The simplified system ························································ 25 2.3-2 Delay buffer and C-element ············································· 26 CHAPTER 3 Multi-Ports Pipelined System 3.1 Previous Approaches ···································································· 29 3.2 Modifying Two-Phase Pipeline System with Symmetric C-element ······················································································· 34 3.2-1 Symmetric C-element without Output Buffer ················ 35 3.2-2 XNOR gate and double-edge-triggered flip-flop ············ 38 3.3 Modified NOR-based Four-Phase Pipeline Protocol ················· 39 3.3-1 NOR mechanism used in the four-phase protocol for multi-port modules ································································· 39 3.3-2 Modifying Implement Input Switches with Symmetric C-element ··············································································· 41 CHAPTER 4 Simulation Results 4.1 Simulation Results of XNOR BASED Double-Edge- Triggered Flip-Flop ···························································································· 43 4.1-1 Conditions ·············································································· 43 4.1-2 Generally Speaking ······························································· 44 4.1-3 Propagation Delay And Power Dissipation ······················ 45 4.1-4 Set-up/Hold Time, and Current Variation······················· 47 4.1-5 Maximum Response Speed in Individual and Pipelined System ······················································································· 48 4.1-6 Performance Comparison ··················································· 52 4.2 Simulation Results of Pipelined System Comparison ·············· 54 4.2-1 Conditions ·············································································· 54 4.2-2 Propagation Delay and Power Dissipation as varying W/L ····························································································· 55 4.2-3 Propagation Delay and Power Dissipation as varying Supply Voltage ········································································· 57 CHAPTER 5 Conclusion and Future Works 5.1 Conclusion ······················································································ 62 5.2 Future Works ·················································································· 64 References ····································································································· 66 Publications ·································································································· 73en-US雙邊緣觸發雙相管線互斥非或閘標示訊號多重輸出入埠非同步double-edge-triggeredtwo-phasepipelineXNORInterlocked Pipelined CMOSSymmetric C-elementStrobeMulti-portAsynchronousthesis