Chen, ChunChunChenLiao, Jeng YuJeng YuLiaoCHIEN-MO LIChen, Harry H.Harry H.ChenFang, Eric Jia WeiEric Jia WeiFang2023-07-142023-07-142023-01-019798350346305https://scholars.lib.ntu.edu.tw/handle/123456789/633636We propose a novel minimum operating voltage (Vmin) prediction method using nondestructive stress test to avoid area overhead and reduce test time. We process stress-test faillogs and generate summation values by three strategies to predict Vmin. In addition, we select important test patterns by Spearman correlation and simulated annealing to reduce test time. Two regression models are adopted in our experiment. Experimental results on advanced 7nm and 3nm chip designs show that the average RMSE of our predict Vmin can be as low as 4.48 mV to 8.66mV by one strategy with linear regression model. Our method gives smaller RMSE than process monitor prediction methods with no area overhead, and is 50 to 62.5 times faster compared to conventional testing.Chip performance prediction | Nondestructive stress test[SDGs]SDG13conference paper10.1109/VTS56346.2023.101400482-s2.0-85161829864https://api.elsevier.com/content/abstract/scopus_id/85161829864