Chen, K.-Y.K.-Y.ChenChen, W.-Y.W.-Y.ChenSHEN-IUAN LIU2020-06-112020-06-11201715497747https://scholars.lib.ntu.edu.tw/handle/123456789/499890https://www.scopus.com/inward/record.uri?eid=2-s2.0-85034259042&doi=10.1109%2fTCSII.2016.2645698&partnerID=40&md5=f901e1678fa5b1be416a5deeb42c84c6This brief presents a low-power 20-Gb/s decision feedback equalizer (DFE) with one discrete tap and two infinite impulse response (IIR) filters feedback. The advantage of the IIR-DFE lies in both great energy and area efficiency for large channel attenuations. To further enhance the power efficiency of the IIR-DFE, the charge-steering logic (CSL) is utilized in this brief. Besides, the quarter-rate topology is adopted to alleviate the race condition of the CSL-based DFE. Fabricated in a 40-nm-LP CMOS process, the DFE core circuits only consumes 6.2 mW from the 1-V supply. Moreover, the core entirely occupies an area of 5700 mu2. Measured with PRBS7, the bit error rates are all less than 10-12 for channel loss from -7.98 to -18.3 dB. Finally, the power efficiency of this IIR-DFE is 0.31 pJ/bit. © 2004-2012 IEEE.Charge-steering logic (CSL); decision feedback equalizer (DFE); infinite impulse response (IIR)[SDGs]SDG7CMOS integrated circuits; Computer circuits; Decision feedback equalizers; Feedback; Impulse response; Area efficiency; Channel attenuation; Channel loss; Charge-steering logic (CSL); CMOS processs; Core circuit; Infinite impulse response; Power efficiency; IIR filtersjournal article10.1109/TCSII.2016.26456982-s2.0-85034259042