公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2023 | A 0.02mm<sup>2</sup>Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology | Cheng, Sheng Jen; Qiu, You Rong; Hong, Chung Hung; Liu, Wei Yi; Li, Chia Hsuan; CHUNG-PING CHEN | 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings | 0 | 0 | |
2005 | 1-V 7-mW Dual-Band Fast-Locked Frequency Synthesizer | Vikas Sharma; Chien-Liang Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN | GLSVLSI | | | |
2011 | A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique | Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Wu, Y.-C.; Lin, B.-F.; Chiu, H.-C.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2013 | A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS | Cheng, W.-S.; Hsieh, M.-H.; Hung, S.-H.; Hung, S.-Y.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2011 | A 12 Gb/s chip-to-chip AC coupled transceiver | Wang, Y.-S.; Hsieh, M.-H.; Wu, Y.-C.; Liu, C.-M.; Chiu, H.-C.; Lin, B.-F.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2015 | A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique | Hung, S.-H.; Kao, W.-H.; Wu, K.-I.; Huang, Y.-W.; Hsieh, M.-H.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2015 | A -194 dBc/Hz FOM interactive current-reused QVCO (ICR-QVCO) with capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique | Wu, K.-I.; Shen, I.-S.; Jou, C.F.; CHUNG-PING CHEN | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | | | |
2012 | A 2 -8 GHz multi-phase distributed DLL using phase insertion in 90 nm | Hsieh, M.-H.; Lin, B.-F.; Wang, Y.-S.; Chang, H.-H.; CHUNG-PING CHEN | ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems | | | |
2002 | 3-D Thermal-ADI: a linear-time chip level transient thermal simulator | Ting-Yuan Wang; CHUNG-PING CHEN | IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD) | | | |
2003 | 3D Thermal-ADI: An Efficient Chip-Level Transient Thermal Simulator | Ting-Yuan Wang; Yu-Min Lee; CHUNG-PING CHEN | ACM International Symposium on Physical Design (ISPD) | | | |
2007 | 3DFFT: Thermal analysis of non-homogeneous IC using 3D FFT green function method | Oh, D.; Chen, C.C.P.; Hu, Y.H.; CHUNG-PING CHEN | Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007 | | | |
2013 | A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology | Liu, P.-K.; Hung, S.-Y.; Liu, C.-Y.; Hsieh, M.-H.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2016 | A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS | Hsieh, M.-H.; Chen, L.-H.; Liu, S.-I.; SHEN-IUAN LIU ; CHUNG-PING CHEN | IEEE Journal of Solid-State Circuits | 19 | 19 | |
2012 | A 6.7MHz-to-1.24GHz 0.0318mm2fast-locking all-digital DLL in 90nm CMOS | Hsieh, M.-H.; Chen, L.-H.; Liu, S.-I.; CHUNG-PING CHEN | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | | | |
2015 | A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme | Chien, A.; Hung, S.-H.; Wu, K.-I.; Liu, C.-Y.; Hsieh, M.-H.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2010 | A Legendre Pseudospectral Frequency-Domain Method for Solving Maxwell’s Equations | C. Y. Wang; S. Y. Chung; C. H. Teng; C. P. Chen; HUNG-CHUN CHANG ; CHUNG-PING CHEN | XX URSI Commission B International Symposium on Electromagnetic Theory (EMT-S 2010) | 1 | 0 | |
2004 | A ROBDD-Based Generalized Nodal Control Scheme for Standby Leakage Power Reduction | Hsinwei Chou; CHUNG-PING CHEN | The 12th Workshop on Synthesis And System Integration of Mixed Information technologies | | | |
2004 | A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling | Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | | | |
2008 | Abbe singular-value decomposition: Compact Abbe's kernel generation for microlithography aerial image simulation using singular-value decomposition method | Chen, C.C.P.; Gurhanli, A.; Chiang, T.-Y.; Hong, J.-J.; Melvin, L.S.; CHUNG-PING CHEN | Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures | | | |
2009 | Abbe-PCA (Abbe-Hopkins): Microlithography aerial image analytical compact kernel generation based on principle component analysis | Tsai, M.-F.; Chang, S.-J.; Chen, C.C.P.; Melvin III, L.S.; CHUNG-PING CHEN | Proceedings of SPIE - The International Society for Optical Engineering | | | |