|Title:||A 0.02mm<sup>2</sup>Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology||Authors:||Cheng, Sheng Jen
Qiu, You Rong
Hong, Chung Hung
Liu, Wei Yi
Li, Chia Hsuan
|Keywords:||current-controlled oscillator | Phase-locked loop | small area | spur reduction | sub-sampling||Issue Date:||1-Jan-2023||Source:||2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings||Abstract:||
In the conventional PLL, the loop filter is composed of passive capacitor which occupies the most parts of chip area. As a result, PLL can save the area by replacing the passive capacitor which stores or releases the charges to a current-controlled oscillator and a dummy oscillator which store the phase information. To reduce the output phase noise, the letter adopts sub-sampling technique. As the loop locks the frequency and the phase difference between reference and divider output is less than 180°, the loop turns off the frequency-locked loop and the sub-sampling phase detector with higher gain dedicates on phase locking. Meanwhile, the loop turns off the divider path so as to avoid the divider from injecting phase noise into the system. However, the sub-sampling technique brings three side effects and lets the reference spur raise up. Hence, this thesis adopts spur reduction technique to alleviate those disadvantages from sub-sampling technique. The proposed PLL is fabricated in TSMC 90nm CMOS technology which active area is 0.02mm2 and provides 2GHz clock. The reference spur is -49.42 dBc and phase noise is -80.32 dBc/Hz at 1MHz offset from carrier frequency under 1.2V power supply with 8.68mW power dissipation.
|Appears in Collections:||電機工程學系|
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