公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2023 | A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing | Lin, Yu Cheng; Park, Chanmin; Zhao, Wenda; Sun, Nan; Chae, Youngcheol; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
2022 | A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality | Huang, Wen Cong; Lin, I. Ting; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 1 | 0 | |
2023 | A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring | Chen, Po Shao; Chen, Yen Lung; Lee, Yu Chi; Fu, Zih Sing; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | | | |
2021 | A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring | CHIA-HSIANG YANG ; Chen P.-S; Chen Y.-L; Lee Y.-C; Fu Z.-S; CHIA-HSIANG YANG | Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference | | | |
2023 | A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow | Du, Cheng Yan; Tsai, Chieh Fu; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 0 | 0 | |
2018 | A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems | C.-H. Chiang; S.-A. Huang; C.-E. Chen; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium Circuits and Systems (ISCAS) | | | |
2018 | A 2กั2-16กั16 Reconfigurable GGMD Processor for MIMO Communication Systems | CHIA-HSIANG YANG ; Chiang, C.-H.; Huang, S.-A.; Chen, C.-E.; CHIA-HSIANG YANG | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2024 | 30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization | Chu, Yi Chen; Lin, Yu Cheng; Lo, Yu Chen; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | | | |
2021 | 4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images | CHIA-HSIANG YANG ; Shen H.-Y; Lee Y.-C; Tong T.-W; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | | | |
2023 | A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing | Lin, Liang Hsin; Fu, Zih Sing; Chen, Po Shao; Yang, Bo Yin; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
2022 | A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training | Fu, Zih Sing; Lee, Yu Chi; Park, Alex; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 3 | 0 | |
2023 | A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator | Shen, Hsueh Yen; Lee, Yu Chi; Tong, Tzu Wei; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 0 | 0 | |
2022 | A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing | Lo, Yu Chen; Wu, Yi Chung; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
2017 | A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications | CHIA-HSIANG YANG ; Li, M.-R.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | | | |
2017 | A 5.28-Gbps LDPC Decoder with Time-domain Signal Processing for IEEE 802.15.3c Applications | M.-R. Li; C.-H. Yang; Y.-L. Ueng; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | | | |
2017 | A 501mW 7.61Gb/s Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MIMO Systems | Y.-T. Chen; C.-C. Cheng; T.-L. Tsai; W.-C. Sun; Y.-L. Ueng; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium on VLSI Circuits (VLSI) | 19 | 0 | |
2017 | A 501mW 7.6lGb/s integrated message-passing detector and decoder for polar-coded massive MIMO systems | CHIA-HSIANG YANG ; Chen Y.-T; Cheng C.-C; Tsai T.-L; Sun W.-C; Ueng Y.-L; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | | | |
2023 | A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition | Tong, Tzu Wei; Hsieh, Yi Yen; Chen, Tai Jung; CHIA-HSIANG YANG | 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023 | | | |
2022 | A 75.6M Base-pairs/s FPGA Accelerator for FM-index Based Paired-end Short-Read Mapping | Yang, Chung Hsuan; Wu, Yi Chung; Chen, Yen Lung; Lee, Chao Hsi; Hung, Jui Hung; CHIA-HSIANG YANG | 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings | 0 | 0 | |
2023 | A 96.2-nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction | Hsieh, Yi Yen; Lin, Yu Cheng; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 1 | 1 | |