https://scholars.lib.ntu.edu.tw/handle/123456789/641965
標題: | 30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization | 作者: | Chu, Yi Chen Lin, Yu Cheng Lo, Yu Chen CHIA-HSIANG YANG |
公開日期: | 1-一月-2024 | 來源出版物: | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 摘要: | Autonomous navigation serves as a versatile technology prominently used in logistics and transportation. The application of automatic guided vehicles has become pervasive within the realm of factory automation, as shown in Fig. 30.4.1. For such applications, path planning and collision avoidance are two main tasks. Both tasks are classified as combinatorial optimization problems (COPs), and finding their optimal solutions is time-consuming [1]. A COP can be mapped to an Ising model with spin couplings based on the nature of the problem. Annealing is then applied to find the solution by iteratively updating spins until the states of the spins reach the lowest energy (known as a Hamiltonian). Digital annealers [2] -[4] have been demonstrated to accelerate solving COPs with exponential complexity. Some designs [2] [3] only support small-scale COPs because of the limited number of spins. The other [4] can solve larger problems, while the problem complexity is still limited by their sparse spin connections. Mapping a COP onto an Ising model and vice versa is necessary for solving a specific problem, which is also not addressed in the previous hardware digital annealers. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/641965 | ISBN: | 9798350306200 | ISSN: | 01936530 | DOI: | 10.1109/ISSCC49657.2024.10454294 |
顯示於: | 電機工程學系 |
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