公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2016 | Data allocating apparatus, signal processing apparatus, and data allocating method | C.-H. Yang; H.-M. Liu; Y.-J. Lin; CHIA-HSIANG YANG | | | | |
2016 | Design of a 0.5V 1.68mW Nose-on-a-Chip for Rapid Screen of Chronic Obstructive Pulmonary Disease | T.-I. Chou; S.-W. Chiu; K.-H. Chang; Y.-J. Chen; C.-T. Tang; C.-H. Shih; C.-C. Hsieh; M.-F. Chang; C.-H. Yang; H. Chiueh; K.-T. Tang; CHIA-HSIANG YANG | IEEE Biomedical Circuits & Systems Conf. (BioCAS) | 0 | 0 | |
2021 | Design of a Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its in Vivo Verification | Liu C.-H; Wu, Chung-Yu; Ker, Ming-Dou; Liu, Chien-Hao ; Hung, Chung-Chih; Yang, Chia-Hsiang ; Lee, Chia-Fone; Chang, Po-Chih; Tu, Yen-Fu; Tang, Li-Yang; Chen, Ching-Yuan; CHIEN-HAO LIU | IEEE Journal of Solid-State Circuits | 12 | 8 | |
2004 | Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems | Yang, Chia-Hsiang ; Lin, Yu-Hsuan; Lin, Shih-Chun; Chiueh, Tzi-Dar | 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04 | 7 | 0 | |
2021 | Design optimization for ADMM-Based SVM Training Processor for Edge Computing | Huang S.-A; Hsieh Y.-Y; CHIA-HSIANG YANG | 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021 | | | |
2018 | Diagnostic Role of Anal Sphincter Relaxation Integral in High-Resolution Anorectal Manometry for Hirschsprung Disease in Infants | JIA-FENG WU ; CHENG-HSUN LU ; CHIA-HSIANG YANG ; I-JUNG TSAI | Journal of Pediatrics | 23 | 10 | |
2020 | Digital Logic and Asynchronous Datapath with Heterogeneous TFET-MOSFET Structure for Ultralow-Energy Electronics | Hung, J.; Wang, P.; Lo, Y.; Yang, C.; Tsui, B.; CHIA-HSIANG YANG | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits | | | |
2018 | Distal contractile to impedance integral ratio assist the diagnosis of pediatric ineffective esophageal motility disorder | JIA-FENG WU ; Chung, Chieh; PING-HUEI TSENG ; I-JUNG TSAI ; Lin, Yi-Cheng; CHIA-HSIANG YANG ; YI-CHENG LIN | Pediatric Research | 4 | 4 | |
2008 | DSP architecture optimization in Matlab/Simulink environment | CHIA-HSIANG YANG ; N; a, R.; Yang, C.-H.; Markovic, D.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | | | |
2016 | Energy Recycling Systems and Recycling Method Thereof | C.-H. Yang; P.-H. Hsieh; C.-Y. Lee; CHIA-HSIANG YANG | | | | |
2023 | An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices | Yu, Sheng Jung; Lee, Yu Chi; Lin, Liang Hsin; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 0 | 0 | |
2016 | Error-resilient sequential cells with successive time borrowing for stochastic computing | Liu, W.-C.; Chan, C.-D.; Huang, S.-A.; Lo, C.-W.; Yang, C.-H.; Jou, S.-J.; CHIA-HSIANG YANG | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | | | |
2017 | Extreme index finder and finding method thereof | M.-R. Li; C.-H. Yang; Y.-L. Ueng; CHIA-HSIANG YANG | | | | |
2017 | A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems | Y.-C. Tsai; C.-E. Chen; C.-H. Yang; CHIA-HSIANG YANG | IEEE Transaction on Circuits & Systems I (TCAS-I) | 5 | 5 | |
2023 | An FM-index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-end Short-read Mapping | Yang, Chung Hsuan; Wu, Yi Chung; Chen, Yen Lung; Lee, Chao Hsi; Hung, Jui Hung; CHIA-HSIANG YANG | IEEE Transactions on Biomedical Circuits and Systems | 0 | 0 | |
2023 | A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing | Chen, Yen Lung; Yang, Chung Hsuan; Wu, Yi Chung; Lee, Chao Hsi; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; Hung, Jui Hung; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 0 | 0 | |
2020 | A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing | Wu, Y.-C.; Chen, Y.-L.; Yang, C.-H.; Lee, C.-H.; Yu, C.-Y.; Chang, N.-S.; Chen, L.-C.; Chang, J.-R.; Lin, C.-P.; Chen, H.-L.; Chen, C.-S.; Hung, J.-H.; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | | | |
2022 | Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression | Kao, Chen Chien; Hsieh, Yi Yen; Chen, Chao Hung; CHIA-HSIANG YANG | Midwest Symposium on Circuits and Systems | 1 | 0 | |
2019 | A Hardware-Efficient ADMM-Based SVM Training Algorithm for Edge Computing. | Huang, Shuo-An; CHIA-HSIANG YANG | CoRR | | | |
2012 | Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection | CHIA-HSIANG YANG ; Shih, Y.-H.; Chen, T.-J.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG | 2012 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012 | | | |