https://scholars.lib.ntu.edu.tw/handle/123456789/633766
標題: | An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices | 作者: | Yu, Sheng Jung Lee, Yu Chi Lin, Liang Hsin CHIA-HSIANG YANG |
關鍵字: | Backward secrecy | cryptographic processor | digital integrated circuit | double ratchet | end-to-end encryption | Internet of Things (IoT) | 公開日期: | 1-六月-2023 | 卷: | 58 | 期: | 6 | 來源出版物: | IEEE Journal of Solid-State Circuits | 摘要: | This work presents the first cryptographic processor that supports the double ratchet protocol with backward secrecy for the Internet-of-Things (IoT) devices. A precomputation-based constant modular divider is used to reduce the area by 39.5% and energy consumption by 18.8%. A hash-based key derivative function (HKDF) module is proposed to reduce the energy consumption of the length selector by 89.8% and the energy consumption of the module by 35% by leveraging the characteristic of the input. A GF(24)2-based S-box is used to reduce the area of S-box by 21.2%. A 1-byte S-box is shared for key generation and text encryption/decryption to reduce the area by 46.8%. Fabricated in a 40-nm CMOS technology, the chip integrates 227k gates in 1.03 mm 2 and dissipates 1.18 mW at 16 MHz from a 0.56-V supply. The chip achieves a 211 734× lower energy consumption than the CPU solution. Compared with the state-of-the-art end-to-end protocol cryptographic processor, this work achieves an 18.5× higher energy efficiency for secure hash algorithm (SHA), 3× higher energy efficiency for advanced encryption standard (AES), and a 41% less energy for protocol establishment, with 10% smaller area. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/633766 | ISSN: | 00189200 | DOI: | 10.1109/JSSC.2022.3220838 |
顯示於: | 電機工程學系 |
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