| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2012 | Obstacle-avoiding free-assignment routing for flip-chip designs | Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | Design Automation Conference | 2 | 0 | |
| 2014 | Obstacle-avoiding free-assignment routing for flip-chip designs | Ho, Y.-K.; Lee, H.-C.; Lee, W.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 9 | |
| 2022 | Obstacle-avoiding multiple redistribution layer routing with irregular structures | Chen, Yen Ting; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
| 2008 | Obstacle-avoiding rectilinear steiner tree construction based on spanning graphs | Chen, S.-Y.; Li, C.-F.; CHIA-LIN YANG ; CHUNG-WEI LIN ; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 53 | 46 | |
| 2019 | Obstacle-aware group-based length-matching routing for pre-assignment area-I/O flip-chip designs | Chang, Y.-H.; Wen, H.-T.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 3 | 0 | |
| 1996 | On a new timing-driven routing tree problem | Wong, D.F.; Zhu, Kai; Wong, C.K.; YAO-WEN CHANG | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | | |
| 2021 | On-Chip Optical Routing with Provably Good Algorithms for Path Clustering and Assignment | Lu Y; Yu S; Chang Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
| 2021 | On-chip Optical Routing with Waveguide Matching Constraints | Chuang F.-Y; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 1 | 0 | |
| 2021 | Opportunities for 2.5/3D Heterogeneous SoC Integration | CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 1 | 0 | |
| 2006 | An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. | Su, Bor-Yiing; Chang, Yao-Wen; Hu, Jiang; YAO-WEN CHANG | Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006 | 7 | 0 | |
| 2007 | An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing | Su, Bor-Yiing; Su, Bor-Yiing; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | 5 |  |
| 2000 | Optimal reliable crosstalk-driven interconnect optimization | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG | International Symposium on Physical Design | 7 | | |
| 2000 | Optimal reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000 | 7 | 0 | |
| 2006 | An optimal simultaneous diode/jumper insertion algorithm for antenna fixing. | Jiang, Zhe-Wei; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
| 2016 | Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process | Liu, Iou-Jen; Fang, Shao-Yun; Chang, Yao-Wen; YAO-WEN CHANG | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 6 | 5 | |
| 2014 | Overlay-Aware detailed routing for self-Aligned double patterning lithography using the cut process | Liu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 25 | 0 | |
| 2008 | Packing Floorplan Representations. | Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG | Handbook of Algorithms for Physical Design Automation. | | | |
| 2001 | Performance optimization by wire and buffer sizing under the transmission line model | Chen, T.-C.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 3 | | |
| 2001 | Performance optimization by wire and buffer sizing under the transmission line model | Chen, Tai-Chen; Pan, Song-Ra; YAO-WEN CHANG | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 3 | 0 | |
| 2002 | Performance Optimization Under the Transmission Line Model | 張耀文 | | | | |
