https://scholars.lib.ntu.edu.tw/handle/123456789/580770
標題: | Opportunities for 2.5/3D Heterogeneous SoC Integration | 作者: | CHUNG-PING CHEN HUI-RU JIANG JIUN-LANG HUANG YAO-WEN CHANG |
關鍵字: | Chip scale packages; Costs; Integration; Printed circuit design; Programmable logic controllers; System-on-chip; VLSI circuits; Circuit designs; Co-design methodology; Design complexity; Electrical effects; Heterogeneous systems; Low-cost packaging; Suboptimal solution; Wafer-level chip scale packages; Integrated circuit design | 公開日期: | 2021 | 來源出版物: | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 摘要: | As the design complexity grows dramatically in modern circuit designs, 2.5D/3D chip/package/board integration has become effective for optimizing system performance and power consumption. Various 2.5D/3D technologies have been explored. Among many technologies, wafer-level chip-scale packages have been adopted by major companies such as TSMC to achieve high-density, high-performance, low-cost packaging solutions. A simple combination of traditional tools is insufficient to achieve the desired design quality for chip-package-board integration of a heterogeneous system, which might lead to suboptimal solutions. Hence, in this work, we study the chip, package, and board codesign methodology with advanced packages and explore key techniques to handle the emerging challenges in physical design, timing, electrical effects, and testing. There are still many opportunities for future research to advance 2.5D/3D heterogeneous SoC integration. ? 2021 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85106600469&doi=10.1109%2fVLSI-DAT52063.2021.9427350&partnerID=40&md5=874980cd99dd3d7a93993bd09930ae84 https://scholars.lib.ntu.edu.tw/handle/123456789/580770 |
DOI: | 10.1109/VLSI-DAT52063.2021.9427350 |
顯示於: | 電機工程學系 |
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