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公開日期
標題
作者
來源出版物
scopus
WOS
全文
2009
Gate Tunneling Leakage Current Behavior of 40nm PD SOI NMOS Device Considerign the Floating Body Effect
H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
International Electron Devices Materials Symposium
2006
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology
B. Chung; J. B. Kuo; JAMES-B KUO
ISCAS
0
0
2006
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
B. Chung; J. B. Kuo; JAMES-B KUO
PATMOS
2008
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application
B. Chung; JAMES-B KUO
Integration, the VLSI Journal
10
10
2008
Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applications
R. Chen; R. Liu; J. B. Kuo; JAMES-B KUO
ICSICT
1
0
2005
Gate-Misalignment Related Capacitance Behavior of a 100nm DG SOI MOS Devices with N+/p+ Top/Bottom Gate
J. B. KUo; C. H. Hsu; C. P. Yang; JAMES-B KUO
HKEDSSC
2017
A General and Transformable Model Platform for Emerging Multi-Gate MOSFETs
Hong C; Zhou J; Huang J; Wang R; Bai W; Kuo J.B; Chen Y.; JAMES-B KUO
IEEE Electron Device Letters
2012
Grain Boundary-Related Kink Effects of Poly-Si TFTs
T. C. Liu; J. B. Kuo; JAMES-B KUO
IEEE International Conference on Electron Devices and Solid State Circuit
1
0
2012
Grain-Boundary Impact Ionization-Induced Current Hump Effects of Polysilicon TFTs
T. C. Liu; J. B. Kuo; S. Zhang; JAMES-B KUO
IEDMS
1995
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems
Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB
ASIC Conference and Exhibit, 1995.
0
0
2000
A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation
Huang Y.-M; JAMES-B KUO
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
12
8
2002
High-Temperature Quasi-Saturation Model of High-Voltage DMOS Power Devices
C. L. Yang; J. B. Kuo; JAMES-B KUO
Hong Kong Electron Devices Meeting
0
0
2007
Influence of STI-induced mechnical stress in kink effect of 65nm PD SOI CMOS devices
I. Lin; V. Su; J. Kuo; R. Lee; G. Lin; D. Chen; C. Yeh; C. Tsai; M. Ma; JAMES-B KUO
Electron Devices and Solid State State Circuits (EDSSC) Conf
1
0
2007
Investigation of Substrate Noise Isolation Solutions in Deep Submicron CMOS Technology
H. Lin; J. Kuo; r. Sobot; M. Syrzycki; JAMES-B KUO
Canadian Conference on Electrical and Computer Engineering
2
0
2014
Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC
G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
Asia Pacific CSEE Conference
1994
Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
Wang, J.Y.; Chen, Y.G.; KuoJB
Electronics Letters
1
0
1999
Low-Voltage CMOS VLSI Circuits
J. B. Kuo; J. H. Lou; JAMES-B KUO
2001
Low-Voltage Content Addressable Memory Cell with a Fast Tag-Compare Capability Using Partially-Depleted SOI CMOS Dynamic-Threshold Techniques
J. B. Kuo; S. C. Liu; JAMES-B KUO
2007
Low-Voltage Single-Phase Clocking Adiabatic DCVS Logic Circuit with Pass Gate Logic
E. K. Loo; J. B. Kuo; M. Syrzycki; JAMES-B KUO
Canadian Conference on Electrical and Computer Engineering
2010
Low-Voltage SOI CMOS DTMOS/MTCMOS Circuit Technique for Design Optimization of Low-power SOC Applications
W.C.H. Lin; J. B. Kuo; JAMES-B KUO
ISCAS
0
0