https://scholars.lib.ntu.edu.tw/handle/123456789/342557
標題: | Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application | 作者: | B. Chung JAMES-B KUO |
關鍵字: | Dual-threshold CMOS; Power optimization; SOC; Static timing analysis | 公開日期: | 一月-2008 | 卷: | 42 | 期: | 1 | 起(迄)頁: | 9-16 | 來源出版物: | Integration, the VLSI Journal | 摘要: | This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications using 90 nm multi-threshold complementory metal oxide semiconductor (MTCMOS) technology. The cell libraries come in fixed threshold-high Vth for good standby power and low Vth for high speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library. © 2007 Elsevier B.V. All rights reserved. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-34548505549&doi=10.1016%2fj.vlsi.2007.03.001&partnerID=40&md5=75c47804f1c7c9b618a697a9cd0475f7 | DOI: | 10.1016/j.vlsi.2007.03.001 |
顯示於: | 電機工程學系 |
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