公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1997 | Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects | Kuo, J.B.; Su, K.W.; KuoJB | IEEE International SOI Conference | 0 | 0 | |
2006 | Compact Gate Tunneling Current Model Considering Distributed Effect for Sub-100nm NMOS Devices with Ultra-thin (1nm) Gate Oxide | C. H. Lin; J. B. Kuo; K. W. Su; S. Liu; JAMES-B KUO | IEDMS | | | |
2002 | Compact LDD/FD SOI CMOS Device Model Considering Energy Transport and Self Heating for SPICE Circuit Simulation | J. B. Kuo; S. C. Lin; JAMES-B KUO | IEDMS | | | |
2009 | Compact Modelign of Nanometer SOI CMOS Devices Considering Shallow Trench Isolation | JAMES-B KUO | NSC Seminar | | | |
2014 | Compact Modeling of 40nm Pd SOI NMOS Devices Considering Floating Body Effect | JAMES-B KUO | MOST Microelectronics Research Seminar | | | |
2011 | Compact Modeling of Nanometer SOI CMOS Devices Considering Shallow Trench Isolation | JAMES-B KUO | NSC Seminar | | | |
2012 | Compact Modeling of SOI CMOS Devices | JAMES-B KUO | NSC Seminar | | | |
2003 | Compact Modeling of SOI CMOS VLSI Devices | JAMES-B KUO | NSC Research Seminar | | | |
2008 | Compact Modeling of Sub-90nm CMOS VLSI Devices Considering Fringing Electric Field Effects | JAMES-B KUO | NSC Seminar | | | |
1999 | Compact MOS/Bipolar Charge-Control Model of Partially-Depleted SOI CMOS Devices for VLSI Circuit Simulation---SOI-Technology (ST)-SPICE | J. B. Kuo; K. W. Su; S. C. Lin; JAMES-B KUO | European Solid State Device Research Conference (ESSDERC) | | | |
2002 | Compact threshold-voltage model for short-channel partially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices | J. B. Kuo; K. H. Yuan; S. C. Lin; JAMES-B KUO | IEEE Transactions on Electron Devices | 7 | 6 | |
1994 | Concise analytical model for deep submicron N-channel metal-oxide-semiconductor devices with consideration of energy transport | Ma S.-Y; JAMES-B KUO | Japanese Journal of Applied Physics | 12 | 11 | |
1995 | Concise short-channel effect model for inversion-type ultrathin silicon-on-insulator p-channel metal-oxide-silicon field-effect transistors based on partitioning of thin-film | Chen S.-S; JAMES-B KUO | Japanese Journal of Applied Physics | 1 | 0 | |
2014 | Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs | G. Lin; J. B. Kuo; JAMES-B KUO | ISCAS | 6 | 0 | |
1992 | Delayed-turn-on phenomenon in accumulation-type SOI pMOS device operating at liquid nitrogen temperature | Kuo, J.B.; Sim, J.H.; KuoJB | Electronics Letters | | | |
2012 | Design of Distortionless Interconnects via Main/auxiliary Structure with LC Line for High Speed On-chip Transmission | T. C. Liu; J. B. Kuo; S. D. Zhang; JAMES-B KUO | ICSICT | | | |
2009 | Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique | C. H. Lin; J. B. Kuo; JAMES-B KUO | Power and Timing Optimization Symposium | | | |
1991 | Device-level analysis of a 1 μm BiCMOS inverter circuit operating at 77 K using a modified PISCES program | Kuo, J.B.; Chen, Y.W.; Lou, K.H.; KuoJB | Custom Integrated Circuits Conference, 1991 | 0 | 0 | |
1994 | Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI | Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB | Custom Integrated Circuits Conference, 1994 | 0 | 0 | |
1991 | Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator | Kuo, J.B.; Chen, Y.W.; KuoJB | Bipolar Circuits and Technology Meeting, 1991. | 0 | 0 | |