公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2018 | Low-Complexity Privacy-Preserving Compressive Analysis Using Subspace-Based Dictionary for ECG Telemonitoring System | Ching-Yao Chou; En-Jui Chang; Huai-Ting Li; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Biomedical Circuits and Systems (TBioCAS) | 32 | 27 | |
2019 | Low-Complexity Recurrent Neural Network-Based Polar Decoder With Weight Quantization Mechanism | Chieh-Fang Teng; Chen-Hsi (Derek) Wu; rew Kuan-Shiuan Ho; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2018) | 11 | 0 | |
2018 | Low-Complexity Secure Watermark Encryption for Compressed Sensing-Based Privacy Preserving | Kai-Ni Hou; Ting-Sheng Chen; Hung-Chi Kuo; Tzu-Hsuan Chen; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Int. Conf. Acoust. Speech, Signal Processing (ICASSP-2018) | 1 | 0 | |
2014 | Low-Complexity Sinusoidal-Assisted EMD (SAEMD) Algorithms for Solving Mode-Mixing Problems in HHT | Wen-Chung Shen; Yu-Hao Chen; AN-YEU(ANDY) WU | Digital Signal Processing(DSP) | 43 | 34 | |
2017 | Low-Complexity Stochastic Gradient Pursuit (SGP) Algorithm and Architecture for Robust Compressive Sensing Reconstruction | Yu-Min Lin; Yi Chen; Nai-Shan Huang; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Signal Processing | 22 | 22 | |
2007 | Low-latency quasi-synchronous transmission technique for multiple-clock-domain IP modules | AN-YEU(ANDY) WU ; Ye, J.-J.; Chen, Y.-G.; Wey, I.-C.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2007 | Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. | Ye, Jhao-Ji; Chen, You-Gang; Wey, I-Chyn; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | | | |
2017 | Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine | Chia-Heng Wu; Ting-Sheng Chen; Ding-Yuan Lee; An-Yeu (Andy) Wu; AN-YEU(ANDY) WU ; 吳安宇 | Int. Symp. VLSI Design, Automation, and Test | 2 | 0 | |
1994 | Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
1994 | A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. | Wu, An-Yeu; Liu, K. J. Ray; AN-YEU(ANDY) WU | 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994 | | | |
1996 | Low-power design methodology for DSP systems using multirate approach | AN-YEU(ANDY) WU ; Wu, An-Yeu; Ray Liu, K.J.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2009 | Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder | Cheng-Hung Lin; Chun-Yu Chen; An-Yeu Wu; Tsung-Han Tsai; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Circuits and Systems Part I: Regular Paper | 41 | 30 | |
2009 | Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder | AN-YEU(ANDY) WU ; Lin, C.-H.; Chen, C.-Y.; Wu, A.-Y.; Tsai, T.-H.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2008 | Low-power traceback MAP decoding for double-binary convolutional turbo decoder | AN-YEU(ANDY) WU ; Lin, C.-H.; Chen, C.-Y.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2023 | Machine-aided PPG Signal Quality Assessment (SQA) for Multi-mode Physiological Signal Monitoring | Beh, Win Ken; Yang, Yu Chia; Lo, Yi Cheng; Lee, Yun Chieh; AN-YEU(ANDY) WU | ACM Transactions on Computing for Healthcare | 0 | 0 | |
2012 | Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders | Min-An Chao; Xin-Yu Shih; AN-YEU(ANDY) WU | Journal of Signal Processing Systems (JSPS) | 3 | 3 | |
2015 | Message from technical program chairs | Takagi, S.; Lian, Y.; AN-YEU(ANDY) WU ; Morie, T. | IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS | 0 | 0 | |
2015 | Method and apparatus for performing channel shortening equalization with frequency notch mitigation | Yen-Liang Chen; Shao-Wei Feng; Cheng-Zhou Zhan; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | | | | |
2023 | Mitigating Non-ideality Issues of Analog Computing-In-Memory in DNN-based designs | Huang, Chi Tse; AN-YEU(ANDY) WU | Proceedings of International Conference on ASIC | | | |
2005 | Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications | AN-YEU(ANDY) WU ; Lin, C.-H.; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |