公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2020 | High Efficiency and Low Overkill Testing for Probabilistic Circuits | CHIEN-MO LI ; Lee M.-T; Wu C.-H; Liu S.-T; Hsieh C.-Y; CHIEN-MO LI | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | | | |
2023 | High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns | Liang, Zhe Jia; Wu, Yu Tsung; Yang, Yun Feng; CHIEN-MO LI ; Chang, Norman; Kumar, Akhilesh; Li, Ying Shiun | Proceedings - International Test Conference | | | |
1998 | IDDQ data analysis using current signature | CHIEN-MO LI ; Li, J.C.M.; McCluskey, E.J.; CHIEN-MO LI | Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998 | | | |
2008 | IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores | CHIEN-MO LI ; Geng-Ming Chiu; C.-Y. Chiu; R-Y. Wen; CHIEN-MO LI | International Test Conference | | | |
2021 | Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization | CHIEN-MO LI ; Wu M.-T; Kuo C.-S; Li J.C.-M; Nigh C; Bhargava G.; CHIEN-MO LI | Proceedings - International Test Conference | | | |
2018 | IR drop prediction of ECO-revised circuits using machine learning | CHIEN-MO LI ; Lin, S.-Y.; Fang, Y.-C.; Li, Y.-C.; Liu, Y.-C.; Yang, T.-S.; Lin, S.-C.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI | Proceedings of the IEEE VLSI Test Symposium | | | |
2005 | Jump Scan: A DFT Technique for Low Power Testing, | CHIEN-MO LI ; M.H. Chiu; CHIEN-MO LI | IEEE VLSI Test Symposium | | | |
2006 | Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique | CHIEN-MO LI ; Y. L Kao; W. S. Chuang; CHIEN-MO LI | IEEE International Test Conference | | | |
2012 | Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains, | CHIEN-MO LI ; JIUN-LANG HUANG ; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG | ACM Transactions on Design Automation of Electronic Systems (TODAES) | | 0 | |
2006 | Logic and fault simulation | Huang, J.-L. ; Li, J.C.-M. ; Walker, D.M. | VLSI Test Principles and Architectures | 0 | 0 | |
2022 | Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor | Liu, Shi Tang; Chen, Jia Xian; Wu, Yu Tsung; Hsieh, Chao Ho; CHIEN-MO LI ; Chang, Norman; Li, Ying Shiun; Chuang, Wen Tze | Proceedings - International Symposium on Quality Electronic Design, ISQED | 0 | 0 | |
2018 | Machine-learning-based dynamic IR drop prediction for ECO | CHIEN-MO LI ; Fang, Y.-C.; Lin, H.-Y.; Su, M.-Y.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
2010 | Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium | CHIEN-MO LI ; J. Y. Wen; CHIEN-MO LI | | | | |
2021 | Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning | CHIEN-MO LI ; Kuo Y.-T; Lin W.-C; Chen C; Hsieh C.-H; Li J.C.-M; Jia-Wei Fang E; Hsueh S.S.-Y.; CHIEN-MO LI | Proceedings - International Test Conference | | | |
2022 | ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption | Lin, Wei Chen; Chen, Chun; Hsieh, Chao Ho; CHIEN-MO LI ; Fang, Eric Jia Wei; Hsueh, Sung S.Y. | Proceedings - International Test Conference | 1 | 0 | |
2012 | Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs | CHIEN-MO LI ; B. C. Bai; CHIEN-MO LI | ITC | | | |
2016 | A multicircuit simulator based on inverse jacobian matrix reuse | CHIEN-MO LI ; Lee, H.-I.; Han, C.-Y.; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
2015 | The Multimedia Piers-Harris Children's Self-Concept Scale 2: Its Psychometric Properties, Equivalence with the Paper-and-Pencil Version, and Respondent Preferences | CHIEN-MO LI ; Flahive, Mon-hsin Wang; Chuang, Ying-Chih; CHIEN-MO LI | Plos One | | | |
2018 | A new method for parameter estimation of high-order polynomial-phase signals. | CHIEN-MO LI ; Cao, Runqing; Li, James Chien-Mo; Zuo, Lei; Wang, Zeyu; Lu, Yunlong; CHIEN-MO LI | Signal Processing | | | |
2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |