公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
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2013 | Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggering | CHIEN-MO LI ; Y. C. Huang; M. H. Tsai; W. S. Ding; J. C. M. Li; M. T. Chang; M. H. Tsai; C. M. Tseng; H. C. Li; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |