Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
---|---|---|---|---|---|---|
2010 | A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm | Chia-Tsun Wu; Wen-Chung Shen; Wei Wang; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Circuits and Systems, Part-II: Express Briefs (SCI, EI) | 48 | 40 |