公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2010 | 3D-PIC: An Error Tolerant 3D CMOS Imager | H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG | 3D Integration Workshop | |||
2013 | A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers | H.-M. Chang; J.-L. Huang; D.-M. Kwai; K.-T. Cheng; C.-W. Wu; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 6 | 6 | |
2011 | A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager | X.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG | European Test Symposium | 5 | 0 | |
2012 | A SAR ADC missing-decision level detection and removal technique | X.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | VLSI Test Symposium | 0 | 0 | |
2011 | A self-testing and calibration method for embedded successive approximation register ADC | X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 11 | 0 | |
2010 | An Error Tolerance Scheme for 3D CMOS Imagers | H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG | Design Automation Conference | 13 | 0 | |
2012 | An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration | X.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 5 | 5 |