公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2010 | Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization | Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 24 | 0 | |
2011 | Escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 11 | 0 | |
2013 | Escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 12 | 11 | |
2013 | Layer minimization in escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 5 | 0 | |
2013 | Multiple chip planning for chip-interposer codesign | Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 28 | 0 | |
2014 | Obstacle-avoiding free-assignment routing for flip-chip designs | Ho, Y.-K.; Lee, H.-C.; Lee, W.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 9 | |
2012 | Obstacle-avoiding free-assignment routing for flip-chip designs | Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | Design Automation Conference | 2 | 0 | |