https://scholars.lib.ntu.edu.tw/handle/123456789/358171
標題: | Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization | 作者: | Shih, X.-W. Cheng, C.-C. Ho, Y.-K. Chang, Y.-W. YAO-WEN CHANG |
公開日期: | 2010 | 起(迄)頁: | 395-400 | 來源出版物: | Asia and South Pacific Design Automation Conference, ASP-DAC | 摘要: | In high-performance nanometer synchronous chip design, a buffered clock tree with high tolerance of process variations is essential. The nominal clock skew always plays a crucial role in determining circuit performance and thus should be a first-order objective for clock-tree synthesis. The clock latency range (CLR), which is the latency difference under different supply voltages, is defined by the 2009 ACM ISPD Clock Network Synthesis Contest as the major optimization objective to measure the effects of process variation on clock-tree synthesis. In this paper, we propose a three-level framework which effectively constructs clock trees by performing blockage-avoiding buffer insertion with both nominal skew and CLR minimization. To cope with the objectives, we present a novel three-stage TTR clock-tree construction algorithm which consists of clock-tree Topology Generation, Tapping-Point Determination, and Routing. Experimental results show that our framework with the TTR algorithm achieves the best average quality for both nominal skew and CLR, compared to all the participating teams for the 2009 ISPD Clock Network Synthesis Contest. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-77951224766&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/358171 |
DOI: | 10.1109/ASPDAC.2010.5419850 | SDG/關鍵字: | Buffer insertion; Chip design; Circuit performance; Clock network synthesis; Clock skews; Clock Tree; Clock-tree synthesis; First-order; Participating teams; Process Variation; Supply voltages; Three-level; Tree construction algorithms; Tree topology; Adaptive systems; Computer aided design; Digital integrated circuits; Electric clocks; Marine risers; Optimization; Telecommunication networks; Trees (mathematics) |
顯示於: | 電子工程學研究所 |
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