公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2004 | A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling | Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | |||
2005 | False Path and Clock Scheduling Based Yield-Aware Gate Sizing | Jeng-Liang Tsai; DongHyun Baik; Charlie Chung-Ping Chen; Kewal K. Saluja; CHUNG-PING CHEN | VLSI Design | |||
2004 | HiSIM: Hierarchical Interconnect-Centric Circuit Simulator | Tsung-Hao Chen; Jeng-Liang Tsai; Charlie Chung-Ping Chen; Tanay Karnik; CHUNG-PING CHEN | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | |||
2004 | Power-Delivery Networks Optimization with Thermal Reliability Integrity | Ting-Yuan Wang; Jeng-Liang Tsai; |CHUNG-PING CHEN | ACM International Symposium on Physical Design (ISPD) | |||
2005 | Process-Variation Robust and Low-Power Zero-Skew Buffered Clock-Tree Synthesis Using Projected Scan-Line Sampling | Jeng-Liang Tsai; CHUNG-PING CHEN | ASPDAC | |||
2005 | Statistical Timing Analysis Driven Post-Silicon-Tunable Clock-Tree Synthesis | Jeng-Liang Tsai; Lizheng Zhang; CHUNG-PING CHEN | ICCAD | |||
2004 | Thermal and Power Integrity based Power/Ground Networks Optimization | Ting-Yuan Wang; Jeng-Liang Tsai; CHUNG-PING CHEN | Design, Automation and Test in Europe Conference and Exhibition (DATE) |