公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2008 | A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays | C.-W. Lin; Jiun-Lang Huang; JIUN-LANG HUANG | VLSI Test Symposium | 11 | 0 | |
2010 | An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and Scaling | Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG | VLSI Test Symposium | 9 | 0 | |
2009 | Analog-to-Digital Converter | Jiun-Lang Huang; Jui-Jer Huang; Chuan-Che Lee; JIUN-LANG HUANG | ||||
2009 | Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC | X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 1 | 0 | |
2010 | CSER: BISER-based concurrent soft-error resilience | CHIEN-MO LI ; JIUN-LANG HUANG ; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; CHIEN-MO LI ; JIUN-LANG HUANG | VLSI Test Symposium (VTS) | |||
2013 | METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAME | Hung-I Chen; Chang-Yu Chen; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG | ||||
2013 | SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN | Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG | ||||
2006 | VLSI Test Principles and Architectures | Laung-Terng Wang; Cheng-Wen Wu; Xiaoqing Wen; Khader S. Abdel-Hafez; Wen-Ben Jone; Rohit Kapur; Brion Keller; Kuen-Jong Lee; CHIEN-MO LI ; Mike Peng Li; Xiaowei Li; T.M. Mak; Yinghua Min; Benoit Nadeau-Dostie; Soumendu Bhattacharya; Mehrdad Nourani; Janusz Rajski; Charles Stroud; Erik H. Volkerink; Duncan M. (Hank) Walker; Shianling Wu; Nur A. Touba; Abhijit Chatterjee; Xinghao Chen; Kwang-Ting (Tim) Cheng; William Eklow; Michael S. Hsiao; Jiun-Lang Huang; Shi-Yu Huang |