Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
---|---|---|---|---|---|---|
2015 | Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits | Chiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 9 | 0 |