公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2023 | A 0.02mm<sup>2</sup>Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology | Cheng, Sheng Jen; Qiu, You Rong; Hong, Chung Hung; Liu, Wei Yi; Li, Chia Hsuan; CHUNG-PING CHEN | 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings | 0 | 0 |