公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2023 | A 0.02mm<sup>2</sup>Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology | Cheng, Sheng Jen; Qiu, You Rong; Hong, Chung Hung; Liu, Wei Yi; Li, Chia Hsuan; CHUNG-PING CHEN | 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings | 0 | 0 | |
2006 | A 0.18μm probabilistic-based noise-tolerate circuit design and implementation with 28.7dB noise-immunity improvement | Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 | | | |
2023 | A 0.25-μm HV-CMOS Synchronous Inversion and Charge Extraction Interface Circuit with a Single Inductor for Piezoelectric Energy Harvesting | Chen, Chi Wei; Pranoto, Weining Zeng; HSIN-SHU CHEN ; WEN-JONG WU | IEEE Transactions on Power Electronics | 0 | | |
2018 | A 0.25�gm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting | Cheng, K.-R.; Chen, H.-S.; Lallart, M.; Wu, W.-J.; WEN-JONG WU | IEEE International Symposium on Circuits and Systems | | | |
2005 | 1-V 7-mW Dual-Band Fast-Locked Frequency Synthesizer | Vikas Sharma; Chien-Liang Chen; Charlie Chung-Ping Chen; CHUNG-PING CHEN | GLSVLSI | | | |
2014 | 1. Precision Engineering and Nanotechnology V
2. Key Engineering Materials Vol. 625 | 陳亮嘉主編; LIANG-CHIA CHEN | | | | |
2011 | 1.2 m Shielded Cassegrain Antenna for Close-Packed Radio Interferometer | Koch, Patrick M.; Raffin, Philippe; Huang, Yau-De; Chen, Ming-Tang; Han, Chih-Chiang; Lin, Kai-Yang; Altamirano, Pablo; Granet, Christophe; Ho, Paul T. P.; Huang, Chih-Wei L.; Kesteven, Michael; Li, Chao-Te; Liao, Yu-Wei; Liu, Guo-Chin; Nishioka, Hiroaki; Ong, Ching-Long; Oshiro, Peter; Umetsu, Keiichi; Wang, Fu-Cheng; JIUN-HUEI PROTY WU ; FU-CHENG WANG | Publications of the Astronomical Society of the Pacific | 4 | 2 | |
2011 | A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique | Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Wu, Y.-C.; Lin, B.-F.; Chiu, H.-C.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2013 | A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS | Cheng, W.-S.; Hsieh, M.-H.; Hung, S.-H.; Hung, S.-Y.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2004 | 1000BASE-T Gigabit Ethernet baseband DSP IC design | Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | | | |
2008 | 10GBase-T乙太網路系統晶片設計-子計畫五:適用於10GBase-T乙太網路之高效能數位信號處理引擎設計(2/3) | 吳安宇 | | | | |
2007 | 10GBase-T乙太網路系統晶片設計-子計畫五:適用於10GBase-T乙太網路之高效能數位信號處理引擎設計(3/3) | 吳安宇 | | | | |
2011 | A 12 Gb/s chip-to-chip AC coupled transceiver | Wang, Y.-S.; Hsieh, M.-H.; Wu, Y.-C.; Liu, C.-M.; Chiu, H.-C.; Lin, B.-F.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2003 | 12吋晶圓廠之分散式系統及排程系統之發展(1/2) | 黃漢邦 | | | | |
2004 | 12吋晶圓廠之分散式系統及排程系統之發展(2/2) | 黃漢邦 | | | | |
2015 | A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique | Hung, S.-H.; Kao, W.-H.; Wu, K.-I.; Huang, Y.-W.; Hsieh, M.-H.; CHUNG-PING CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2020 | 170-nm Tuning Range and Low-Threshold Cr4+:YAG Double-Clad Crystal Fiber Laser | Li Y.-H; Lin Y.-C; Hsu Y.-W; Yang T.-I; Huang S.-L.; SHENG-LUNG HUANG | Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS | 0 | | |
2020 | 170-nm tuning range and low-threshold Cr4+:YAG double-clad crystal fiber laser | Li Y.-H; Lin Y.-C; Hsu Y.-W; Yang T.-I; Huang S.-L.; SHENG-LUNG HUANG | Optics InfoBase Conference Papers | 0 | 0 | |
2019 | A 180-nm Tunable Ti:sapphire Crystal Fiber Laser for OCT Applications | Kuo, C.-Y.; Huang, S.-L.; Donati, S.; SHENG-LUNG HUANG | 2019 IEEE International Conference on BioPhotonics, BioPhotonics 2019 | 0 | 0 | |
2015 | A -194 dBc/Hz FOM interactive current-reused QVCO (ICR-QVCO) with capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique | Wu, K.-I.; Shen, I.-S.; Jou, C.F.; CHUNG-PING CHEN | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | | | |