第 1 到 46 筆結果,共 46 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2015 | Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems | Chang, En-Jui; Hsin, Hsien-Kai; Chao, Chih-Hao; Lin, Shu-Yen; Wu, An-Yeu; AN-YEU(ANDY) WU ; SHU-YEN LIN | Ieee Transactions on Computers | 28 | 26 | |
2 | 2009 | Adaptive Channel-Shortened Interpolated Echo and NEXT Canceller Designs Applied to 10GBASE-T Ethernet System | Chen, Yen-Liang; Zhan, Cheng-Zhou; Jheng, Ting-Jyun; Wu, An-Yeu | International Journal of Electrical Engineering | |||
3 | 2009 | Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits | Wey, I-Chyn; Chen, You-Gang; Yu, Chang-Hong; Wu, An-Yeu ; Chen, Jie | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
4 | 2009 | Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor | Lin, Shu-Yen ; Shen, Wen-Chung; Hsu, Chan-Cheng; Wu, An-Yeu | International Journal of Electrical Engineering | |||
5 | 2007 | A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. | Chao, Chih-Hao; Kuo, Yen-Lin; Wu, An-Yeu; Chien, Weber; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | |||
6 | 2007 | Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. | Rao, Huifei; Chen, Jie; Yu, Changhong; Ang, Woon Tiong; Wey, I-Chyn; Wu, An-Yeu; Zhao, Hong; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | |||
7 | 2007 | Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems. | Yu, Tzu-Hao; Sun, Shih-Yu; Ding, Chih-Liang; Li, Pai-Chi; Wu, An-Yeu; PAI-CHI LI ; AN-YEU(ANDY) WU | Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China | 8 | 0 | |
8 | 2006 | A portable all-digital pulsewidth control loop for SOC applications | Wang, Wei; Wey, I-Chyn; Wu, Chia-Tsun; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
9 | 2006 | A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time | Wu, Chia-Tsun; Wang, Wei; Wey, I-Chyn; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
10 | 2006 | DSP engine design for LINC wireless transmitter systems. | Jheng, Kai-Yuan; Wang, Yi-Chiuan; Wu, An-Yeu; HEN-WAI TSAO ; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece | 0 | 0 | |
11 | 2005 | Polar transmitter for wireless communication system | Chen, Chung-Chun; Ko, Hung-Yang; Wang, Yi-Chiuan; Tsao, Hen-Wai ; Jheng, Kai-Yuan; Wu, An-Yeu | 2005 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2005 | 0 | 0 | |
12 | 2005 | A new stopping criterion for efficient early termination in turbo decoder designs | Li, Fan-Min; Wu, An-Yeu | 2005 International Symposium on Intelligent Signal Processing and Communication Systems | 0 | 0 | |
13 | 2004 | Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel | Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu | IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS | 0 | 0 | |
14 | 2004 | Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems | Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu | IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | 0 | 0 | |
15 | 2004 | Least squares approximation-based ROM-free direct digital frequency synthesizer | Wen, Ching-Hua; Hsu, Huai-Yi; Ko, Hung Yang; Wu, An-Yeu | International Symposium on Circuits and Systems, 2004. ISCAS '04 | |||
16 | 2004 | 1000BASE-T Gigabit Ethernet baseband DSP IC design | Lin, Hsiu-Ping; Chen, Nancy F.; Lai, Jyh-Ting; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | |||
17 | 2004 | VLSI design of dual-mode Viterbi/turbo decoder for 3GPP | Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | |||
18 | 2004 | A scalable Reed-Solomon decoding processor based on unified finite-field processing element design | Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
19 | 2004 | Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design | Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
20 | 2003 | Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems | Kuo, Jen-Chih; Wen, Ching-Hua; Wu, An-Yeu | 2003 International Symposium on Circuits and Systems. ISCAS '03 | 0 | 0 | |
21 | 2003 | Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for scaling-free high-performance rotational operations | Lin, Zhi-Xiu; Wu, An-Yeu | IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003 | 0 | 0 | |
22 | 2003 | Angle quantization approach for lattice IIR filter implementation and its trellis de-allocation algorithm | Wu, An-Yeu ; Lee, I-Hsien; Wu, Cheng-Shing | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | 0 | 0 | |
23 | 2003 | A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm | Hsu, Huai-Yi; Wang, Sheng-Feng; Wu, An-Yeu | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology | 2 | 1 | |
24 | 2003 | A Novel Echo Cancellation Algorithm and Architecture Based on Multi-Path Adaptive Interpolated FIR Filter | Wu, Cheng-Shing; Wu, An-Yeu | Journal of the Chinese Institute of Electrical Engineering | |||
25 | 2003 | A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes | AN-YEU(ANDY) WU ; Wu, Cheng-Shing; Wu, An-Yeu; Lin, Chih-Hsiu; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | |||
26 | 2003 | VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems | Kuo, Jen-Chih; Wen, Ching-Hua; Lin, Chih-Hsiu; Wu, An-Yeu | Eurasip Journal on Applied Signal Processing | 45 | 33 | |
27 | 2002 | A Unified View for Vector Rotational CORDIC Algorithms and Architectures Based on Angle Quantization Approach | Wu, An-Yeu ; Wu, Cheng-Shing | IEEE Transactions on Circuits and Systems Part I | |||
28 | 2002 | High-performance adaptive decision feedback equalizer based on predictive parallel branch slicer scheme | Yang, Meng-Da; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
29 | 2002 | A new pipelined adaptive DFE architecture with improved convergence rate | Yang, Meng-Da; Wu, An-Yeu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
30 | 2002 | A Reduced-complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems | Chan, Tsun-Shan; Kuo, Jen-Chih; Wu, An-Yeu | EURASIP Journal on Applied Signal Processing | 3 | 2 | |
31 | 2001 | A very low-cost multi-mode Reed Solomon decoder based on Peterson-Gorenstein-Zierler algorithm | Wang, Sheng-Feng; Hsu, Huai-Yi; Wu, An-Yeu | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 0 | 0 | |
32 | 2001 | A cost-effective TEQ algorithm for ADSL systems | Wang, Chih-Chi; Wu, An-Yeu ; Wang, Bor-Min | IEEE International Conference on Communications | 0 | 0 | |
33 | 1998 | Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology. | Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98, Seattle, Washington, USA, May 12-15, 1998 | |||
34 | 1998 | Transform-domain delayed LMS algorithm and architecture | AN-YEU(ANDY) WU ; Wu, An-Yeu; Wu, Cheng-Shing; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
35 | 1998 | Optimal fixed-point VLSI structure of a floating-point based digital filter design | AN-YEU(ANDY) WU ; Wu, An-Yeu; Hwang, Kuo-Fuo; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
36 | 1998 | Fast algorithm for reduced-complexity programmable DSP implementation of the IFFT/FFT in DMT systems | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; Wang, Bowen; AN-YEU(ANDY) WU | IEEE Global Telecommunications Conference | |||
37 | 1998 | Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
38 | 1998 | Computationally efficient fast algorithm and architecture for the IFFT/FFT in DMT/OFDM systems | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
39 | 1996 | Parallel programmable video co-processor design | AN-YEU(ANDY) WU ; Wu, An-Yeu; Ray Liu, K.J.; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | IEEE International Conference on Image Processing | |||
40 | 1996 | Low-power design methodology for DSP systems using multirate approach | AN-YEU(ANDY) WU ; Wu, An-Yeu; Ray Liu, K.J.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | |||
41 | 1995 | Parallel programmable video co-processor design. | Wu, An-Yeu; Liu, K. J. Ray; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995 | |||
42 | 1995 | Algorithm-based low-power transform coding architectures. | Wu, An-Yeu; Liu, K. J. Ray; AN-YEU(ANDY) WU | 1995 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '95, Detroit, Michigan, USA, May 08-12, 1995 | |||
43 | 1995 | Algorithm-based low-power transform coding architectures | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
44 | 1995 | Algorithm-based low-power DSP system design: Methodology and verification | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | IEEE Workshop on VLSI Signal Processing | |||
45 | 1994 | A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. | Wu, An-Yeu; Liu, K. J. Ray; AN-YEU(ANDY) WU | 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994 | |||
46 | 1994 | Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems |