https://scholars.lib.ntu.edu.tw/handle/123456789/147113
標題: | 互補式金氧半延遲鎖定迴路在時脈合成器與時間至數位轉換器之設計與應用 Design and Application of CMOS DLL in Clock Synthesizers and Time-to-Digital Converters |
作者: | 黃崇禧 Hwang, Chorng-Sii |
關鍵字: | 延遲鎖定迴路;時間至數位轉換器;時脈合成器;clock synthesizer;delay-locked loop;time-to-digital converter | 公開日期: | 2004 | 摘要: | 本論文旨在敘述延遲鎖定迴路(Delay-Locked Loop)以互補式金氧半導體(CMOS)技術來解決時脈合成與時間取樣的問題。文章內容主要分成兩部分。第一部份主要針對延遲鎖定迴路技術應用於類環狀振盪器型式的時脈合成器時,所遭遇之頻率無法改變的問題進行研究。其肇因於當循環式延遲線所造成的全部延遲超過於相位偵測器的捕捉範圍,延遲鎖定迴路之負迴路機制無法回復至其近似鎖定狀態。一個採用雙迴路方式可簡化鎖定偵測器的設計且適用於類比與數位的架構被提出與驗證。另一個使用單迴路方式含頻率偵測器的架構亦被提出,以增進時脈對稱性。此項研究可使採用延遲鎖定迴路設計的時脈合成器可完全相容於傳統鎖相迴路(Phase-Locked Loop)所設計的時脈合成器。第二部份係利用延遲鎖定迴路可提供準確的時序特性,用來設計時間至數位轉換器。於基本電路架構限制下,時間取樣的解析度會被限制於單一個延遲緩衝器的延遲時間。為提高時間精度,並同時兼具快速轉換的特性,一種採用閘延遲差異的平行時間取樣架構被提出。另一個採用二階段轉換方式的時間至數位轉換器,使用多相位取樣方式將時間有效切割後,再利用游標尺式延遲線高解析度特性,可大量節省實作時所需的電路。最後,一種用來提供細微時間差的雙延遲鎖定迴路亦被提出,以供細微時間轉換。 The main goal of this dissertation is to apply the CMOS delay-locked loop (DLL) technique to solve the problems occurred in clock synthesis and time digitization. It is divided into two parts. The first part of this text discusses the design of ROSC-type (Ring Oscillator) clock synthesizers based on DLL. Whenever the frequency changes from high to low according to the system request, the ROSC-type clock synthesizers may suffer from the false-locking situation due to the limited capture range of the phase detector. A design using two-loop architecture is proposed and verified. It possesses the merit of simplifying the design of the necessary lock detector, which guarantees the correct loop behavior. Both digital and analog approaches are feasible in the proposed two-loop architecture. A design using single-loop architecture with a frequency detector is also presented to enhance the matching property between generated clock pulses. The proposed DLL-based clock synthesizers can be functionally compatible with the conventional PLL-based ones. The second part is dedicated to discuss the design of the time-to-digital converter (TDC) by employing the accurate timing provided by DLL. Due to intrinsic limitation of circuit architecture, the resolution of time digitization will be limited to the delay of one unit delay buffer if a set of multi-phase clocks are produced by a simple DLL. A parallel sampling architecture for time interpolation by utilizing the technique of gate delay difference is proposed to be equipped with fast conversion property and a sub-gate resolution. Then, a two-level conversion scheme by employing the multi-phase sampling and vernier delay line (VDL) sampling techniques is presented. It can save the circuit number to implement the pure VDL circuitry if the same dynamic range is desired. Finally, a dual DLL is proposed to provide the mean of regulating the delay difference for fine time interpolation. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/52961 | 其他識別: | en-US |
顯示於: | 電機工程學系 |
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ntu-93-D84523005-1.pdf | 23.31 kB | Adobe PDF | 檢視/開啟 |
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