| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2023 | A 0.0072-mm<sup>2</sup>10-bit 100-MS/s Calibration-free SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS | Tsai, Yao Hung; SHEN-IUAN LIU | 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings | | | |
| 2023 | A 0.02mm<sup>2</sup>Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology | Cheng, Sheng Jen; Qiu, You Rong; Hong, Chung Hung; Liu, Wei Yi; Li, Chia Hsuan; CHUNG-PING CHEN | 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings | | | |
| 2017 | A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer with an Adaptation Time of 2.68 μs | Chen, K.-Y.; Chen, W.-Y.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 8 | 8 | |
| 2004 | A 0.1-23-GHz SiGe BiCMOS analog multiplier and mixer based on attenuation-compensation technique | Tsai, Ming-Da; Lin, Chin-Shen; Wang, Chi-Hsueh; Lien, Chun-Hsien; Wang, Huei | Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE | 0 | 0 |  |
| 1992 | A 0.1-W W-band pseudomorphic HEMT MMIC power amplifier | Chen, T.H.; Tan, K.L.; Dow, G.S.; Wang, H.; Chang, K.W.; Ton, T.N.; Allen, B.; Berenz, J.; Liu, P.H.; Streit, D.; Hayashibara, G.; HUEI WANG | GaAs IC Symposium Technical Digest 1992 | 22 | 0 | |
| 2006 | A 0.18μm probabilistic-based noise-tolerate circuit design and implementation with 28.7dB noise-immunity improvement | Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 | 22 | 0 | |
| 2001 | 0.24-μm CMOS technology and BSIM RF modeling for bluetooth power applications | Chen, Y.-J.E.; Heo, D.; Laskar, J.; Bien, D.; YI-JAN EMERY CHEN | Microwave Journal | 1 | | |
| 2018 | A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting | Kai-Ren Cheng; Hsin-Shu Chen; Micka?l Lallart; Wen-Jong Wu; HSIN-SHU CHEN | IEEE ISCAS | 6 | 0 | |
| 2017 | A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillator | Chang, C.-K.; Tsai, Y.-K.; Cheng, K.-H.; Lu, L.-H.; LIANG-HUNG LU | Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017 | 0 | 0 | |
| 2017 | A 0.31-pJ/bit 20-Gb/s DFE with 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS | Chen, K.-Y.; Chen, W.-Y.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 15 | 15 | |
| 2015 | A 0.33 V 683 μW K-band transformer-based receiver front-end in 65 nm CMOS technology | Cheng, J.-H.; Hsieh, C.-L.; Wu, M.-H.; Tsai, J.-H.; Huang, T.-W.; TIAN-WEI HUANG | IEEE Microwave and Wireless Components Letters | 12 | 11 | |
| 2015 | A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS | Hsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU | Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 | 16 | 0 | |
| 2015 | A 0.43pJ/bit true random number generator | Kuan, T.-K.; Chiang, Y.-H.; Liu, S.-I.; SHEN-IUAN LIU | Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 | 21 | 0 | |
| 2003 | A 0.5-14-GHz 10.6-dB CMOS cascode distributed amplifier | Liu, Ren-Chieh; Lin, Chin-Shen; Deng, Kuo-Liang; Wang, Huei | VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on | | | |
| 2007 | A 0.5-V 1.9-GIk low-power phase-locked loop in 0.18-μm CMOS | Hsieh, H.-H.; Lu, C.-T.; LIANG-HUNG LU ; LIANG-HUNG LU | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 37 | 0 | |
| 2009 | 0.5-V 5.6-GHz CMOS receiver subsystem | Chen, H.-C.; Wang, T.; Chiu, H.-W.; Kao, T.-H.; Lu, S.-S.; SHEY-SHI LU | IEEE Transactions on Microwave Theory and Techniques | | | |
| 2020 | A 0.5-V, 1.79-μW, 250-kbps Wake-up Receiver for IoT application in 90-nm CMOS | Zhang Z.-C; Chiu C.-Y; Yuan H.-C; TSUNG-HSIEN LIN | 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 | 2 | 0 | |
| 2018 | A 0.55THz Y-Vector Network Configured Beam Steering Phased Array in CMOS Technology | Zhao, Y.; Hadi, R.A.; Lu, H.-C.; Tseng, T.-S.; Zhang, Y.; Qiao, W.; Lo, M.K.; Jou, C.-P.; Zhang, K.; Chang, M.-C.F.; HSIN-CHIA LU | IEEE MTT-S International Microwave Symposium Digest | 2 | 0 | |
| 2009 | 0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications | W. J. H. Lin; C. Y. Chien; J. B. Kuo; JAMES-B KUO | EUROSOI | | | |
| 2019 | A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System | Yao-Sheng Hu; Li-Yu Huang; Hsin-Shu Chen; HSIN-SHU CHEN | IEEE Journal of Solid-State Circuits | 4 | 5 | |
