DC 欄位 | 值 | 語言 |
dc.contributor | Dept. of Electr. Eng., National Taiwan Univ. | en |
dc.contributor.author | LIANG-GEE CHEN | en |
dc.contributor.author | Chen, T.H. | en |
dc.creator | Chen, L.G.; Chen, T.H. | en |
dc.date | 1991-07 | en |
dc.date.accessioned | 2007-04-19T03:21:08Z | - |
dc.date.accessioned | 2018-07-06T09:46:41Z | - |
dc.date.available | 2007-04-19T03:21:08Z | - |
dc.date.available | 2018-07-06T09:46:41Z | - |
dc.date.issued | 1991-07 | - |
dc.identifier | 1350-2387 | en |
dc.identifier.issn | 01437062 | en |
dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032509 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0026190265&doi=10.1049%2fip-e.1991.0036&partnerID=40&md5=f663d148923606b539a2bd07f898f10d | - |
dc.description.abstract | The paper presents a novel fault-tolerant circuit design using a time-redundancy method for a serial-parallel multiplier, which is useful in DSP applications with serial data transmission. It utilises the RECO (Recomputing with Circularly shifted Operands) technique to detect errors concurrently. A simple OR-gate based circuit is used as the location table to identify faulty bit-slice pairs. The reconfiguration technique is then introduced to bypass the potential faulty bit-slices. This design can have the maximum detectable error region (≅n/2 bits), without appending extra computing elements. The latency from error detection to location is only about two clock cycles, i.e. almost real-time detecting can be achieved. Pipelined timing for two computations is illustrated. The analyses of performance and complexity are described. The results show that this is an efficient design methodology for fault-tolerant multiplication with serial data. | - |
dc.format | application/pdf | en |
dc.format.extent | 447548 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.language | en-US | en |
dc.language.iso | en_US | - |
dc.relation | Computers and Digital Techniques, IEE Proceedings- | en |
dc.relation.ispartof | IEE Proceedings E: Computers and Digital Techniques | - |
dc.subject.other | Computer systems, Digital--Fault tolerant capability; Data Transmission--Computer Applications; Logic devices--Gates; Signal processing--Digital techniques; Fault-Tolerant Serial-Parallel Multiplier; Faulty Bit-Slice Pairs Identification; OR-Gate Based Circuit; Recomputing With Circularly Shifted Operands (RECO); Serial Data Transmission; Time-Redundancy Method; Computers | - |
dc.title | Fault-tolerant serial-parallel multiplier | en |
dc.type | journal article | en |
dc.identifier.doi | 10.1049/ip-e.1991.0036 | - |
dc.identifier.scopus | 2-s2.0-0026190265 | - |
dc.relation.pages | 276 - 280 | - |
dc.relation.journalvolume | 138 | - |
dc.relation.journalissue | 4 | - |
dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/2007041910032509/1/00081907.pdf | - |
item.languageiso639-1 | en_US | - |
item.cerifentitytype | Publications | - |
item.fulltext | with fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.openairetype | journal article | - |
item.grantfulltext | open | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Networking and Multimedia | - |
crisitem.author.orcid | 0000-0001-9746-9355 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系
|