dc.relation.reference | [1] C. J. Alpert, J. Hu, S. S. Sapatnekar, and C. N. Sze, Accurate Estimation
of Global Bu®er Delay within a Floorplan," in Proceeding of International
Conference on Computer Aided Design, pp. 1140-1146, 2004.
[2] S.-C. Chang, C.-T. Hsieh, and K.-C. Wu, Re-synthesis for Delay Varia-
tion Tolerance," in Proceeding of Design Automation Conference, pp. 814-819,
2004.
[3] K. Chaudhary and M. Pedram, A Near Optimal Algorithm for Technology
Mapping Minimizing Area under Delay Constraints," in Proceeding of Design
Automation Conference, pp. 492-498, 1992.
[4] J. Cong and Y. Ding, An Optimal Technology Mapping Algorithm for De-
lay Optimization in Lookup-table Based FPGA Designs," in Proceeding of
International Conference on Computer Aided Design, pp. 48-53, 1992.
[5] Faraday Technology Corporation, http://www.faraday-tech.com/index.html.
[6] L. P. P P. van Ginneken. Bu®er Placement in Distributed RC-tree Networks
for Minimal Elmore Delay," in Proceeding of International Symposium on Cir-
cuits and Systems, pp. 865-868, 1990.
[7] Z. Li, W. Shi, An O(mn) Time Algorithm for Optimal Bu®er Insertion of Nets
With m Sinks," in Proceeding of Asia and South Paci‾c Design Automation
Conference, pp. 320-325, 2006.
[8] D.-J. Jongeneel, Y. Watanbe, R. K. Brayton, and R. Otten, Area and Search
Space Control for Technology Mapping," in Proceeding of Design Automation
Conference, pp. 86-91, 2000.
[9] K.Keutzer, DAGON: Technology Binding and Local Optimization by DAG
Matching," in Proceeding of Design Automation Conference, pp. 617-623,
1987.
[10] Y. Kukimoto, R. K. Brayton, and P. Sawkar, Delay-optimal Technology Map-
ping by DAG Covering," in Proceeding of Design Automation Conference, pp.
348-351, 1998.
[11] T. Kutzschebauch and L. Stok, Congestion Aware Layout Driven Logic Syn-
thesis," in Proceeding of International Conference on Computer Aided Design,
pp. 216-223, 2001.
[12] T. Kutzschebauch and L. Stok, Layout Driven Decomposition with Conges-
tion Consideration," in Proceeding of Design Automation and Test in Europe,
pp.672-676, 2002.
[13] E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness, Logic Decomposi-
tion during Technology Mapping," In Proceeding of International Conference
on Computer Aided Design, pp. 264-271, 1995.
[14] I.-M. Liu, A. Aziz, D.F. Wong, and H. Zhou, An E±cient Bu®er Insertion Al-
gorithm for Large Networks Based on Lagrangian Relaxation," In Proceeding
of International Conference on Computer Design, pp. 614-621, 1999.
[15] I.-M. Liu, A. Aziz, and D.F. Wong, Meeting Delay Constraints in DSM by
Minimal Repeater Insertion," In Proceeding of Design Automation and Test
in Europe, pp. 436-440, 2000.
[16] Q. Liu and M. Marek-Sadowska, Pre-layout Wire Length and Congestion
Estimation," In Proceeding of Design Automation Conference, pp. 582-587,
2004.
[17] Q. Liu and M. Marek-Sadowska, Technology Mapping: Wire Length
Prediction-based Technology Mapping and Fanout Optimization," in Proceed-
ing of International Symposium on Physical Design, pp. 145-151, 2005.
[18] J. Lou, W. Chen, and M. Pedram, Concurrent Logic Restructuring and Place-
ment for Timing Closure", in Proceeding of International Conference on Com-
puter Aided Design, pp. 31-36, 1999.
[19] A. Lu, G. Stenz, and F. M. Johannes, Technology Mapping for Minimizing
Gate and Routing Area," in Proceeding of Design Automation and Test in
Europe, pp. 664-669, 1998.
[20] Y. Matsunaga, On Accelerating Pattern Matching for Technology Mapping,"
in Proceeding of International Conference on Computer Aided Design, pp. 118-
122, 1998.
[21] A. Mishchenko, X. Wang, and T. Kam, A New Enhanced Constructive De-
composition and Mapping Algorithm," in Proceeding of Design Automation
Conference, pp. 143-148, 2003.
[22] M. Murofushi, T. Ishioka, M. Murakata and T. Mitsuhashi, Layout Driven
Re-synthesis for Low Power Consumption LSIs", in Proceeding of Design Au-
tomation Conference, pp. 666-669, 1997.
[23] MVSIS: Logic Synthesis and Veri‾cation,
http://embedded.eecs.berkeley.edu/Respep/Research/mvsis.
[24] D. Pandini, L. T. Pileggi, and A. J. Strojwas, Understanding and Addressing
the Impact of Wiring Congestion during Technology Mapping," in Proceeding
of International Symposium on Physical Design, pp. 131-136, 2002.
[25] D. Pandini, L. Pileggi, and A. Strojwas, Congestion-aware Logic Synthesis,"
in Proceeding of Design Automation and Test in Europe, pp. 664-671, 2002.
[26] M. Pedram and N. Bhat, Layout Driven Technology Mapping," in Proceeding
of Design Automation Conference, pp. 99-105, 1991.
[27] R. S. Shelar, P. Saxena, X. Wang, and S. S. Sapatnekar, Technology Map-
ping: An E±cient Technology Mapping Algorithm Targeting Routing Con-
gestion under Delay Constraints," in Proceeding of International Symposium
on Physical Design, pp. 137-144, 2005.
[28] W. Shi and Z. Li, An O(nlogn) Time Algorithm for Optimal Bu®er Insertion,"
in Proceeding of Design Automation Conference, pp. 580-585, 2003.
[29] C. N. Sze, C. J. Alpert, J. Hu, and W. Shi, Path Based Bu®er Insertion," in
Proceeding of Design Automation Conference, pp. 509-514, 2005.
[30] M. Zhao and S. S. Sapatnekar, A New Structural Pattern Matching Algo-
rithm for Technology Mapping," in Proceeding of Design Automation Confer-
ence, pp. 371-376, 2001. | en |