https://scholars.lib.ntu.edu.tw/handle/123456789/149319
標題: | The Chip design of A 32-b logarithmic number system | 作者: | Huang, Sheng-Chieh LIANG-GEE CHEN Chen Thou-Ho |
公開日期: | 六月-1994 | 卷: | 4 | 起(迄)頁: | 167 - 170 | 來源出版物: | Proceedings - IEEE International Symposium on Circuits and Systems | 會議論文: | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) | 摘要: | To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/2007041910032469 https://www.scopus.com/inward/record.uri?eid=2-s2.0-0028564085&partnerID=40&md5=abfabf8162a0a2cee8966608a09781fe |
ISSN: | 02714310 | 其他識別: | N/A | DOI: | 10.1109/ISCAS.1994.409224 | SDG/關鍵字: | Approximation theory; Digital arithmetic; Electric network analysis; Iterative methods; Logic design; Number theory; Table lookup; Digit partition; Hybrid number system; Iterative difference by linear approximation; Logarithmic number system; Microprocessor chips |
顯示於: | 電機工程學系 |
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00409224.pdf | 338.48 kB | Adobe PDF | 檢視/開啟 |
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