https://scholars.lib.ntu.edu.tw/handle/123456789/152228
Title: | 超大型?米積體電?無格線式全晶片繞線系統 (1/3) Gridless Full-Chip Routing for Very-Large Scale Nanometer ICs | Authors: | 張耀文 | Keywords: | routing;gridless router;multilevel;crosstalk;antenna effect;optical proximity correction (OPC);phase shift mask (PSM);metal filling;繞線;無格線繞線器;多階層;可繞?;?音;天線效應;光學製程修正技術;相位轉移光罩;?屬填充;?屬電子偏移 | Issue Date: | 31-Jul-2005 | Publisher: | 臺北市:國立臺灣大學電機工程學系暨研究所 | Abstract: | 由於多階層繞線的架構擁有可彈性處理極大型積體 電路的良好特性,近幾年被受到很大的重視及研究。目 前文獻上的多階層繞線器大多基於以格線為基礎的模 型,且只考慮可繞度和效能(例如我們於ICCAD-2002 所 提出的以格線為基礎的多階層繞線器 MR [21],以通用 的測試檔測試,具有文獻上最高的可繞度---因此獲得該 會議最佳論文獎提名)。然而,在奈米積體電路技術下, 設計最佳化需要能處理較精細的幾何圖形(如可變線寬 以及可變線距等),而以格線為基礎的模型卻無法有效 地處理許多重要的奈米電氣效應,如訊號完整性(如串 音)、可靠度(如天線效應、金屬電子偏移)以及可製 造性(如光學製程修正技術、相位轉移光罩、金屬填充) 等。在此為期三年的計畫中,我們將 (1) 提出上述奈米 電氣效應的模型,(2) 針對上述的效應,提出最佳化的 方法,及 (3) 發展一套以訊號完整性、可靠度,以及可 製造性為導向,並且能處理極大型積體電路、以無格線 為基礎的多階層全晶片繞線器。 The multilevel routing framework has attracted much attention recently due to its excellent scalability to handle very large-scale circuit designs. Most existing multilevel routers are based on the gridded model and consider only routability and performance. (For example, our work [21] presents a multilevel gridded-based router, called MR, which obtains the highest routability in the literature, based on a set of commonly used benchmark circuits---The work was nominated Best Paper at ICCAD-2002.) However, the grid-based model is not effective to handle many nanometer electrical effects suchas signal integrity (e.g., crosstalk), reliability (e.g., antenna effects, metal electromigration), manufacturability (e.g., optical proximity correction, phase shift mask, metal filling), for which more sophisticated geometrical patterns such as variable wire widths and variable wire spacing are needed for design optimization. In this three-year project, we intend to (1) model those important nanometer electrical effects, (2) derive optimization schemes for them, and (3) develop a signal integrity-, reliability-, and manufacturability-aware multilevel, gridless full-chip routing system for very large-scale nanometer IC designs. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/8051 http://ntur.lib.ntu.edu.tw/bitstream/246246/8051/1/932215E002029.pdf |
Other Identifiers: | 932215E002029 | Rights: | 國立臺灣大學電機工程學系暨研究所 |
Appears in Collections: | 電機工程學系 |
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932215E002029.pdf | 351.86 kB | Adobe PDF | View/Open |
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