https://scholars.lib.ntu.edu.tw/handle/123456789/154789
標題: | Parallel embedded block coding architecture for JPEG 2000 | 作者: | Fang, Hung-Chi Chang, Yu-Wei Wang, Tu-Chih Lian, Chung-Jr LIANG-GEE CHEN |
關鍵字: | Discrete wavelet transform (DWT); Ebc with optimized truncation (EBCOT); Embedded block coding (EBC); Image processing; JPEG 2000; Parallel processing | 公開日期: | 2005 | 卷: | 15 | 期: | 9 | 起(迄)頁: | 1086-1097 | 來源出版物: | IEEE Transactions on Circuits and Systems for Video Technology | 摘要: | This paper presents a parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000. The architecture is based on the proposed word-level EBC algorithm. By processing all the bit planes in parallel, the state variable memories for the context formation (CF) can be completely eliminated. The length of the FIFO (first-in first-out) between the CF and the arithmetic encoder (AE) is optimized by a reconfigurable FIFO architecture. To reduce the hardware cost of the parallel architecture, we proposed a folded AE architecture. The parallel EBC architecture can losslessly process 54 MSamples/s at 81 MHz, which can support HDTV 720p resolution at 30 frames/s. © 2005 IEEE. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/141450 https://www.scopus.com/inward/record.uri?eid=2-s2.0-27644533964&doi=10.1109%2fTCSVT.2005.852618&partnerID=40&md5=c7af7780e17dc7f1578060e81b6a5218 |
ISSN: | 10518215 | DOI: | 10.1109/TCSVT.2005.852618 | SDG/關鍵字: | Discrete wavelet transforms (DWT); Ebc with optimized truncation (EBCOT); Embedded block coding (EBC); JPEG 2000; Parallel processing; Computer architecture; Computer science; Embedded systems; Encoding (symbols); Information technology; Optimization; Parallel processing systems; Wavelet transforms; Block codes |
顯示於: | 電機工程學系 |
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