https://scholars.lib.ntu.edu.tw/handle/123456789/324056
標題: | Multilevel routing with jumper insertion for antenna avoidance | 作者: | Ho, T.-Y. YAO-WEN CHANG SAO-JIE CHEN |
關鍵字: | Design for manufacturability; Multilevel optimization; Routing | 公開日期: | 2006 | 卷: | 39 | 期: | 4 | 起(迄)頁: | 420-432 | 來源出版物: | Integration, the VLSI Journal | 摘要: | As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences reliability, manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high-density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using built-in jumper insertion approach. Compared with the state-of-the-art multilevel routing, the experimental results show that our approach reduced 100% antenna-violated gates and results in fewer wirelength, vias, and delay increase. © 2005 Elsevier B.V. All rights reserved. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-33646530718&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/324056 |
ISSN: | 01679260 | DOI: | 10.1016/j.vlsi.2005.08.005 | SDG/關鍵字: | Algorithms; Antennas; Integrated circuits; Plasma devices; VLSI circuits; Deep-submicron technology; Design for manufacturability; High-density plasma; Multilevel optimization; Routing; Routers |
顯示於: | 電子工程學研究所 |
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