https://scholars.lib.ntu.edu.tw/handle/123456789/362396
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, C.-M. | en_US |
dc.contributor.author | Chen, Y.-J. | en_US |
dc.contributor.author | Lu, Y.-C. | en_US |
dc.contributor.author | Lin, C.-Y. | en_US |
dc.contributor.author | Chen, L.-G. | en_US |
dc.contributor.author | Chien, S.-Y. | en_US |
dc.contributor.author | LIANG-GEE CHEN | zz |
dc.contributor.author | SHAO-YI CHIEN | zz |
dc.creator | Chang, C.-M.;Chen, Y.-J.;Lu, Y.-C.;Lin, C.-Y.;Chen, L.-G.;Chien, S.-Y. | - |
dc.date.accessioned | 2018-09-10T08:34:21Z | - |
dc.date.available | 2018-09-10T08:34:21Z | - |
dc.date.issued | 2011 | - |
dc.identifier.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-84863017330&partnerID=MN8TOARS | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/362396 | - |
dc.description.abstract | A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor is designed and implemented for mobile multimedia applications. It is fabricated in 65nm CMOS technology with core size of 7.56mm 2. The buffer bridged scheduler, energy efficient transaction technique and approximated rendering scheme are proposed to efficiently utilize energy to deliver excessive graphics rendering performance of 1.2Gvertices/s and 2.4Gpixels/s for 3D graphics applications. Moreover, configurable filtering unit (CFU) is also employed for accelerating image processing. Compared with state-of-the-art image signal processors (ISPs), 1.1 times to 7.2 times performance can be achieved by the proposed mobile graphics processor with CFU. © 2011 IEEE. | - |
dc.language | en | en |
dc.relation.ispartof | IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 | - |
dc.source | AH | - |
dc.subject.classification | [SDGs]SDG7 | - |
dc.subject.other | 3D graphics; 3D graphics processor; 65nm CMOS technology; Configurable; Core size; Energy efficient; Graphics rendering; Image signal; Mobile graphics; Mobile multimedia applications; CMOS integrated circuits; Energy efficiency; Image processing; Three dimensional; Three dimensional computer graphics | - |
dc.title | A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor for mobile multimedia applications | - |
dc.type | conference paper | en |
dc.identifier.doi | 10.1109/ASSCC.2011.6123602 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
dc.relation.pages | 405-408 | - |
item.openairetype | conference paper | - |
item.fulltext | no fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Networking and Multimedia | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Intel-NTU Connected Context Computing Center | - |
crisitem.author.dept | Networking and Multimedia | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0001-9746-9355 | - |
crisitem.author.orcid | 0000-0002-0634-6294 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: International Research Centers | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電機工程學系 |
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